sram.tan.qmsg

基于altera ep2c8双口RAM

{ "Info" "ITDB_TSU_RESULT" "altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a0~portb_address_reg5 wraddress\[5\] wrclock 7.461 ns memory " "Info: tsu for memory \"altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a0~portb_address_reg5\" (data pin = \"wraddress\[5\]\", clock pin = \"wrclock\") is 7.461 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.354 ns + Longest pin memory " "Info: + Longest pin to memory delay is 10.354 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns wraddress\[5\] 1 PIN PIN_59 32 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_59; Fanout = 32; PIN Node = 'wraddress\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { wraddress[5] } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(9.244 ns) + CELL(0.176 ns) 10.354 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a0~portb_address_reg5 2 MEM M4K_X11_Y13 0 " "Info: 2: + IC(9.244 ns) + CELL(0.176 ns) = 10.354 ns; Loc. = M4K_X11_Y13; Fanout = 0; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a0~portb_address_reg5'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.420 ns" { wraddress[5] altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a0~portb_address_reg5 } "NODE_NAME" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 56 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.110 ns ( 10.72 % ) " "Info: Total cell delay = 1.110 ns ( 10.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.244 ns ( 89.28 % ) " "Info: Total interconnect delay = 9.244 ns ( 89.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.354 ns" { wraddress[5] altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a0~portb_address_reg5 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.354 ns" { wraddress[5] {} wraddress[5]~combout {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a0~portb_address_reg5 {} } { 0.000ns 0.000ns 9.244ns } { 0.000ns 0.934ns 0.176ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 56 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wrclock destination 2.939 ns - Shortest memory " "Info: - Shortest clock path from clock \"wrclock\" to destination memory is 2.939 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns wrclock 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'wrclock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { wrclock } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns wrclock~clkctrl 2 COMB CLKCTRL_G1 480 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G1; Fanout = 480; COMB Node = 'wrclock~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { wrclock wrclock~clkctrl } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.832 ns) + CELL(0.878 ns) 2.939 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a0~portb_address_reg5 3 MEM M4K_X11_Y13 0 " "Info: 3: + IC(0.832 ns) + CELL(0.878 ns) = 2.939 ns; Loc. = M4K_X11_Y13; Fanout = 0; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a0~portb_address_reg5'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.710 ns" { wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a0~portb_address_reg5 } "NODE_NAME" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 56 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.968 ns ( 66.96 % ) " "Info: Total cell delay = 1.968 ns ( 66.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.971 ns ( 33.04 % ) " "Info: Total interconnect delay = 0.971 ns ( 33.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.939 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a0~portb_address_reg5 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.939 ns" { wrclock {} wrclock~combout {} wrclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a0~portb_address_reg5 {} } { 0.000ns 0.000ns 0.139ns 0.832ns } { 0.000ns 1.090ns 0.000ns 0.878ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.354 ns" { wraddress[5] altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a0~portb_address_reg5 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.354 ns" { wraddress[5] {} wraddress[5]~combout {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a0~portb_address_reg5 {} } { 0.000ns 0.000ns 9.244ns } { 0.000ns 0.934ns 0.176ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.939 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a0~portb_address_reg5 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.939 ns" { wrclock {} wrclock~combout {} wrclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a0~portb_address_reg5 {} } { 0.000ns 0.000ns 0.139ns 0.832ns } { 0.000ns 1.090ns 0.000ns 0.878ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "rdclock q\[6\] altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a6 13.612 ns memory " "Info: tco from clock \"rdclock\" to destination pin \"q\[6\]\" through memory \"altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a6\" is 13.612 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclock source 2.899 ns + Longest memory " "Info: + Longest clock path from clock \"rdclock\" to source memory is 2.899 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns rdclock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'rdclock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclock } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns rdclock~clkctrl 2 COMB CLKCTRL_G2 418 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 418; COMB Node = 'rdclock~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { rdclock rdclock~clkctrl } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.855 ns) + CELL(0.815 ns) 2.899 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a6 3 MEM M4K_X11_Y3 1 " "Info: 3: + IC(0.855 ns) + CELL(0.815 ns) = 2.899 ns; Loc. = M4K_X11_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a6'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.670 ns" { rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a6 } "NODE_NAME" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 248 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.905 ns ( 65.71 % ) " "Info: Total cell delay = 1.905 ns ( 65.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.994 ns ( 34.29 % ) " "Info: Total interconnect delay = 0.994 ns ( 34.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.899 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a6 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.899 ns" { rdclock {} rdclock~combout {} rdclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a6 {} } { 0.000ns 0.000ns 0.139ns 0.855ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 248 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.453 ns + Longest memory pin " "Info: + Longest memory to pin delay is 10.453 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.109 ns) 0.109 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a6 1 MEM M4K_X11_Y3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X11_Y3; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a6'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a6 } "NODE_NAME" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 248 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.987 ns) + CELL(0.624 ns) 3.720 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|mux_0kb:mux5\|result_node\[6\]~198 2 COMB LCCOMB_X26_Y8_N20 1 " "Info: 2: + IC(2.987 ns) + CELL(0.624 ns) = 3.720 ns; Loc. = LCCOMB_X26_Y8_N20; Fanout = 1; COMB Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|mux_0kb:mux5\|result_node\[6\]~198'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.611 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a6 altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|mux_0kb:mux5|result_node[6]~198 } "NODE_NAME" } } { "db/mux_0kb.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/mux_0kb.tdf" 29 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.497 ns) + CELL(3.236 ns) 10.453 ns q\[6\] 3 PIN PIN_41 0 " "Info: 3: + IC(3.497 ns) + CELL(3.236 ns) = 10.453 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'q\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.733 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|mux_0kb:mux5|result_node[6]~198 q[6] } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.969 ns ( 37.97 % ) " "Info: Total cell delay = 3.969 ns ( 37.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.484 ns ( 62.03 % ) " "Info: Total interconnect delay = 6.484 ns ( 62.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.453 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a6 altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|mux_0kb:mux5|result_node[6]~198 q[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.453 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a6 {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|mux_0kb:mux5|result_node[6]~198 {} q[6] {} } { 0.000ns 2.987ns 3.497ns } { 0.109ns 0.624ns 3.236ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.899 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a6 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.899 ns" { rdclock {} rdclock~combout {} rdclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a6 {} } { 0.000ns 0.000ns 0.139ns 0.855ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.453 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a6 altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|mux_0kb:mux5|result_node[6]~198 q[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.453 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a6 {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|mux_0kb:mux5|result_node[6]~198 {} q[6] {} } { 0.000ns 2.987ns 3.497ns } { 0.109ns 0.624ns 3.236ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|address_reg_a\[0\] rdaddress\[12\] rdclock -0.074 ns register " "Info: th for register \"altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|address_reg_a\[0\]\" (data pin = \"rdaddress\[12\]\", clock pin = \"rdclock\") is -0.074 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclock destination 2.787 ns + Longest register " "Info: + Longest clock path from clock \"rdclock\" to destination register is 2.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns rdclock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'rdclock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclock } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns rdclock~clkctrl 2 COMB CLKCTRL_G2 418 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 418; COMB Node = 'rdclock~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { rdclock rdclock~clkctrl } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.666 ns) 2.787 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|address_reg_a\[0\] 3 REG LCFF_X26_Y8_N5 1 " "Info: 3: + IC(0.892 ns) + CELL(0.666 ns) = 2.787 ns; Loc. = LCFF_X26_Y8_N5; Fanout = 1; REG Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|address_reg_a\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.558 ns" { rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|address_reg_a[0] } "NODE_NAME" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 47 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 63.01 % ) " "Info: Total cell delay = 1.756 ns ( 63.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.031 ns ( 36.99 % ) " "Info: Total interconnect delay = 1.031 ns ( 36.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|address_reg_a[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { rdclock {} rdclock~combout {} rdclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|address_reg_a[0] {} } { 0.000ns 0.000ns 0.139ns 0.892ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 47 15 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.167 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.167 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns rdaddress\[12\] 1 PIN PIN_90 3 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_90; Fanout = 3; PIN Node = 'rdaddress\[12\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdaddress[12] } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.460 ns) 3.167 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|address_reg_a\[0\] 2 REG LCFF_X26_Y8_N5 1 " "Info: 2: + IC(1.607 ns) + CELL(0.460 ns) = 3.167 ns; Loc. = LCFF_X26_Y8_N5; Fanout = 1; REG Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|address_reg_a\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.067 ns" { rdaddress[12] altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|address_reg_a[0] } "NODE_NAME" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 47 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.560 ns ( 49.26 % ) " "Info: Total cell delay = 1.560 ns ( 49.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 50.74 % ) " "Info: Total interconnect delay = 1.607 ns ( 50.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.167 ns" { rdaddress[12] altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|address_reg_a[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.167 ns" { rdaddress[12] {} rdaddress[12]~combout {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|address_reg_a[0] {} } { 0.000ns 0.000ns 1.607ns } { 0.000ns 1.100ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|address_reg_a[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { rdclock {} rdclock~combout {} rdclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|address_reg_a[0] {} } { 0.000ns 0.000ns 0.139ns 0.892ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.167 ns" { rdaddress[12] altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|address_reg_a[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.167 ns" { rdaddress[12] {} rdaddress[12]~combout {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|address_reg_a[0] {} } { 0.000ns 0.000ns 1.607ns } { 0.000ns 1.100ns 0.460ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}