sram.tan.qmsg

基于altera ep2c8双口RAM

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "rdclock " "Info: Assuming node \"rdclock\" is an undefined clock" {  } { { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 47 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "rdclock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "wrclock " "Info: Assuming node \"wrclock\" is an undefined clock" {  } { { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 50 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "wrclock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "rdclock memory memory altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a7~porta_address_reg3 altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a7 163.03 MHz Internal " "Info: Clock \"rdclock\" Internal fmax is restricted to 163.03 MHz between source memory \"altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a7~porta_address_reg3\" and destination memory \"altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a7\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.641 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a7~porta_address_reg3 1 MEM M4K_X27_Y9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X27_Y9; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a7~porta_address_reg3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7~porta_address_reg3 } "NODE_NAME" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 280 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.641 ns) 3.641 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a7 2 MEM M4K_X27_Y9 1 " "Info: 2: + IC(0.000 ns) + CELL(3.641 ns) = 3.641 ns; Loc. = M4K_X27_Y9; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a7'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7~porta_address_reg3 altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7 } "NODE_NAME" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 280 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.641 ns ( 100.00 % ) " "Info: Total cell delay = 3.641 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7~porta_address_reg3 altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.641 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7~porta_address_reg3 {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7 {} } { 0.000ns 0.000ns } { 0.000ns 3.641ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.020 ns - Smallest " "Info: - Smallest clock skew is -0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclock destination 2.848 ns + Shortest memory " "Info: + Shortest clock path from clock \"rdclock\" to destination memory is 2.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns rdclock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'rdclock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclock } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns rdclock~clkctrl 2 COMB CLKCTRL_G2 418 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 418; COMB Node = 'rdclock~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { rdclock rdclock~clkctrl } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.804 ns) + CELL(0.815 ns) 2.848 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a7 3 MEM M4K_X27_Y9 1 " "Info: 3: + IC(0.804 ns) + CELL(0.815 ns) = 2.848 ns; Loc. = M4K_X27_Y9; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a7'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.619 ns" { rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7 } "NODE_NAME" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 280 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.905 ns ( 66.89 % ) " "Info: Total cell delay = 1.905 ns ( 66.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.943 ns ( 33.11 % ) " "Info: Total interconnect delay = 0.943 ns ( 33.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.848 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.848 ns" { rdclock {} rdclock~combout {} rdclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7 {} } { 0.000ns 0.000ns 0.139ns 0.804ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rdclock source 2.868 ns - Longest memory " "Info: - Longest clock path from clock \"rdclock\" to source memory is 2.868 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns rdclock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'rdclock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rdclock } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns rdclock~clkctrl 2 COMB CLKCTRL_G2 418 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 418; COMB Node = 'rdclock~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { rdclock rdclock~clkctrl } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.804 ns) + CELL(0.835 ns) 2.868 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a7~porta_address_reg3 3 MEM M4K_X27_Y9 1 " "Info: 3: + IC(0.804 ns) + CELL(0.835 ns) = 2.868 ns; Loc. = M4K_X27_Y9; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a7~porta_address_reg3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.639 ns" { rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7~porta_address_reg3 } "NODE_NAME" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 280 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.925 ns ( 67.12 % ) " "Info: Total cell delay = 1.925 ns ( 67.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.943 ns ( 32.88 % ) " "Info: Total interconnect delay = 0.943 ns ( 32.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7~porta_address_reg3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { rdclock {} rdclock~combout {} rdclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7~porta_address_reg3 {} } { 0.000ns 0.000ns 0.139ns 0.804ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.848 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.848 ns" { rdclock {} rdclock~combout {} rdclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7 {} } { 0.000ns 0.000ns 0.139ns 0.804ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7~porta_address_reg3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { rdclock {} rdclock~combout {} rdclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7~porta_address_reg3 {} } { 0.000ns 0.000ns 0.139ns 0.804ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 280 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 280 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7~porta_address_reg3 altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.641 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7~porta_address_reg3 {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7 {} } { 0.000ns 0.000ns } { 0.000ns 3.641ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.848 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.848 ns" { rdclock {} rdclock~combout {} rdclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7 {} } { 0.000ns 0.000ns 0.139ns 0.804ns } { 0.000ns 1.090ns 0.000ns 0.815ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { rdclock rdclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7~porta_address_reg3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { rdclock {} rdclock~combout {} rdclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7~porta_address_reg3 {} } { 0.000ns 0.000ns 0.139ns 0.804ns } { 0.000ns 1.090ns 0.000ns 0.835ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7 {} } { 0.000ns } { 0.109ns } "" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 280 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "wrclock memory memory altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a16~portb_datain_reg0 altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a16~portb_memory_reg0 163.03 MHz Internal " "Info: Clock \"wrclock\" Internal fmax is restricted to 163.03 MHz between source memory \"altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a16~portb_datain_reg0\" and destination memory \"altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a16~portb_memory_reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.913 ns + Longest memory memory " "Info: + Longest memory to memory delay is 2.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a16~portb_datain_reg0 1 MEM M4K_X11_Y14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y14; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a16~portb_datain_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 568 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.913 ns) 2.913 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a16~portb_memory_reg0 2 MEM M4K_X11_Y14 0 " "Info: 2: + IC(0.000 ns) + CELL(2.913 ns) = 2.913 ns; Loc. = M4K_X11_Y14; Fanout = 0; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a16~portb_memory_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.913 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_datain_reg0 altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 568 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.913 ns ( 100.00 % ) " "Info: Total cell delay = 2.913 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.913 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_datain_reg0 altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_memory_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.913 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_datain_reg0 {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_memory_reg0 {} } { 0.000ns 0.000ns } { 0.000ns 2.913ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.037 ns - Smallest " "Info: - Smallest clock skew is -0.037 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wrclock destination 2.895 ns + Shortest memory " "Info: + Shortest clock path from clock \"wrclock\" to destination memory is 2.895 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns wrclock 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'wrclock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { wrclock } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns wrclock~clkctrl 2 COMB CLKCTRL_G1 480 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G1; Fanout = 480; COMB Node = 'wrclock~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { wrclock wrclock~clkctrl } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.821 ns) 2.895 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a16~portb_memory_reg0 3 MEM M4K_X11_Y14 0 " "Info: 3: + IC(0.845 ns) + CELL(0.821 ns) = 2.895 ns; Loc. = M4K_X11_Y14; Fanout = 0; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a16~portb_memory_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.666 ns" { wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 568 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.911 ns ( 66.01 % ) " "Info: Total cell delay = 1.911 ns ( 66.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.984 ns ( 33.99 % ) " "Info: Total interconnect delay = 0.984 ns ( 33.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.895 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_memory_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.895 ns" { wrclock {} wrclock~combout {} wrclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_memory_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.821ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wrclock source 2.932 ns - Longest memory " "Info: - Longest clock path from clock \"wrclock\" to source memory is 2.932 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns wrclock 1 CLK PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 1; CLK Node = 'wrclock'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { wrclock } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns wrclock~clkctrl 2 COMB CLKCTRL_G1 480 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G1; Fanout = 480; COMB Node = 'wrclock~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { wrclock wrclock~clkctrl } "NODE_NAME" } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.858 ns) 2.932 ns altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a16~portb_datain_reg0 3 MEM M4K_X11_Y14 1 " "Info: 3: + IC(0.845 ns) + CELL(0.858 ns) = 2.932 ns; Loc. = M4K_X11_Y14; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|ram_block2a16~portb_datain_reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.703 ns" { wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 568 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.948 ns ( 66.44 % ) " "Info: Total cell delay = 1.948 ns ( 66.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.984 ns ( 33.56 % ) " "Info: Total interconnect delay = 0.984 ns ( 33.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.932 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_datain_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.932 ns" { wrclock {} wrclock~combout {} wrclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_datain_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.858ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.895 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_memory_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.895 ns" { wrclock {} wrclock~combout {} wrclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_memory_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.821ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.932 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_datain_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.932 ns" { wrclock {} wrclock~combout {} wrclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_datain_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.858ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 568 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 568 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.913 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_datain_reg0 altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_memory_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.913 ns" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_datain_reg0 {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_memory_reg0 {} } { 0.000ns 0.000ns } { 0.000ns 2.913ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.895 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_memory_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.895 ns" { wrclock {} wrclock~combout {} wrclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_memory_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.821ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.932 ns" { wrclock wrclock~clkctrl altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_datain_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.932 ns" { wrclock {} wrclock~combout {} wrclock~clkctrl {} altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_datain_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.845ns } { 0.000ns 1.090ns 0.000ns 0.858ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_memory_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a16~portb_memory_reg0 {} } {  } {  } "" } } { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 568 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}