sram.map.qmsg

基于altera ep2c8双口RAM

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 14 08:31:37 2009 " "Info: Processing started: Tue Apr 14 08:31:37 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sram -c sram " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sram -c sram" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "sram.vhd 2 1 " "Warning: Using design file sram.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sram-SYN " "Info: Found design unit 1: sram-SYN" {  } { { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 57 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sram " "Info: Found entity 1: sram" {  } { { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sram " "Info: Elaborating entity \"sram\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"altsyncram:altsyncram_component\"" {  } { { "sram.vhd" "altsyncram_component" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 100 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"altsyncram:altsyncram_component\"" {  } { { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 100 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_pfn1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pfn1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_pfn1 " "Info: Found entity 1: altsyncram_pfn1" {  } { { "db/altsyncram_pfn1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_pfn1.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_pfn1 altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated " "Info: Elaborating entity \"altsyncram_pfn1\" for hierarchy \"altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_d7t1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_d7t1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_d7t1 " "Info: Found entity 1: altsyncram_d7t1" {  } { { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 31 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_d7t1 altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1 " "Info: Elaborating entity \"altsyncram_d7t1\" for hierarchy \"altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\"" {  } { { "db/altsyncram_pfn1.tdf" "altsyncram1" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_pfn1.tdf" 38 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "clocken1 " "Warning: Variable or input pin \"clocken1\" is defined but never used" {  } { { "db/altsyncram_d7t1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 38 2 0 } } { "db/altsyncram_pfn1.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_pfn1.tdf" 38 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } } { "sram.vhd" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/sram.vhd" 100 0 0 } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_1oa.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_1oa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_1oa " "Info: Found entity 1: decode_1oa" {  } { { "db/decode_1oa.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/decode_1oa.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_1oa altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|decode_1oa:decode3 " "Info: Elaborating entity \"decode_1oa\" for hierarchy \"altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|decode_1oa:decode3\"" {  } { { "db/altsyncram_d7t1.tdf" "decode3" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 50 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_1oa altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|decode_1oa:decode_b " "Info: Elaborating entity \"decode_1oa\" for hierarchy \"altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|decode_1oa:decode_b\"" {  } { { "db/altsyncram_d7t1.tdf" "decode_b" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 53 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_0kb.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_0kb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_0kb " "Info: Found entity 1: mux_0kb" {  } { { "db/mux_0kb.tdf" "" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/mux_0kb.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_0kb altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|mux_0kb:mux5 " "Info: Elaborating entity \"mux_0kb\" for hierarchy \"altsyncram:altsyncram_component\|altsyncram_pfn1:auto_generated\|altsyncram_d7t1:altsyncram1\|mux_0kb:mux5\"" {  } { { "db/altsyncram_d7t1.tdf" "mux5" { Text "F:/毕业设计/毕业设计软件/FPGA/ram/db/altsyncram_d7t1.tdf" 54 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "116 " "Info: Implemented 116 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "46 " "Info: Implemented 46 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "22 " "Info: Implemented 22 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_RAMS" "32 " "Info: Implemented 32 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "164 " "Info: Allocated 164 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 14 08:31:44 2009 " "Info: Processing ended: Tue Apr 14 08:31:44 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}