sram.hier_info

基于altera ep2c8双口RAM

address_b[9] => ram_block2a26.PORTBADDR9
address_b[9] => ram_block2a27.PORTBADDR9
address_b[9] => ram_block2a28.PORTBADDR9
address_b[9] => ram_block2a29.PORTBADDR9
address_b[9] => ram_block2a30.PORTBADDR9
address_b[9] => ram_block2a31.PORTBADDR9
address_b[10] => ram_block2a0.PORTBADDR10
address_b[10] => ram_block2a1.PORTBADDR10
address_b[10] => ram_block2a2.PORTBADDR10
address_b[10] => ram_block2a3.PORTBADDR10
address_b[10] => ram_block2a4.PORTBADDR10
address_b[10] => ram_block2a5.PORTBADDR10
address_b[10] => ram_block2a6.PORTBADDR10
address_b[10] => ram_block2a7.PORTBADDR10
address_b[10] => ram_block2a8.PORTBADDR10
address_b[10] => ram_block2a9.PORTBADDR10
address_b[10] => ram_block2a10.PORTBADDR10
address_b[10] => ram_block2a11.PORTBADDR10
address_b[10] => ram_block2a12.PORTBADDR10
address_b[10] => ram_block2a13.PORTBADDR10
address_b[10] => ram_block2a14.PORTBADDR10
address_b[10] => ram_block2a15.PORTBADDR10
address_b[10] => ram_block2a16.PORTBADDR10
address_b[10] => ram_block2a17.PORTBADDR10
address_b[10] => ram_block2a18.PORTBADDR10
address_b[10] => ram_block2a19.PORTBADDR10
address_b[10] => ram_block2a20.PORTBADDR10
address_b[10] => ram_block2a21.PORTBADDR10
address_b[10] => ram_block2a22.PORTBADDR10
address_b[10] => ram_block2a23.PORTBADDR10
address_b[10] => ram_block2a24.PORTBADDR10
address_b[10] => ram_block2a25.PORTBADDR10
address_b[10] => ram_block2a26.PORTBADDR10
address_b[10] => ram_block2a27.PORTBADDR10
address_b[10] => ram_block2a28.PORTBADDR10
address_b[10] => ram_block2a29.PORTBADDR10
address_b[10] => ram_block2a30.PORTBADDR10
address_b[10] => ram_block2a31.PORTBADDR10
address_b[11] => ram_block2a0.PORTBADDR11
address_b[11] => ram_block2a1.PORTBADDR11
address_b[11] => ram_block2a2.PORTBADDR11
address_b[11] => ram_block2a3.PORTBADDR11
address_b[11] => ram_block2a4.PORTBADDR11
address_b[11] => ram_block2a5.PORTBADDR11
address_b[11] => ram_block2a6.PORTBADDR11
address_b[11] => ram_block2a7.PORTBADDR11
address_b[11] => ram_block2a8.PORTBADDR11
address_b[11] => ram_block2a9.PORTBADDR11
address_b[11] => ram_block2a10.PORTBADDR11
address_b[11] => ram_block2a11.PORTBADDR11
address_b[11] => ram_block2a12.PORTBADDR11
address_b[11] => ram_block2a13.PORTBADDR11
address_b[11] => ram_block2a14.PORTBADDR11
address_b[11] => ram_block2a15.PORTBADDR11
address_b[11] => ram_block2a16.PORTBADDR11
address_b[11] => ram_block2a17.PORTBADDR11
address_b[11] => ram_block2a18.PORTBADDR11
address_b[11] => ram_block2a19.PORTBADDR11
address_b[11] => ram_block2a20.PORTBADDR11
address_b[11] => ram_block2a21.PORTBADDR11
address_b[11] => ram_block2a22.PORTBADDR11
address_b[11] => ram_block2a23.PORTBADDR11
address_b[11] => ram_block2a24.PORTBADDR11
address_b[11] => ram_block2a25.PORTBADDR11
address_b[11] => ram_block2a26.PORTBADDR11
address_b[11] => ram_block2a27.PORTBADDR11
address_b[11] => ram_block2a28.PORTBADDR11
address_b[11] => ram_block2a29.PORTBADDR11
address_b[11] => ram_block2a30.PORTBADDR11
address_b[11] => ram_block2a31.PORTBADDR11
address_b[12] => address_reg_b[0].DATAIN
address_b[12] => decode_1oa:decode4.data[0]
address_b[12] => decode_1oa:decode_b.data[0]
clock0 => ram_block2a0.CLK0
clock0 => ram_block2a1.CLK0
clock0 => ram_block2a2.CLK0
clock0 => ram_block2a3.CLK0
clock0 => ram_block2a4.CLK0
clock0 => ram_block2a5.CLK0
clock0 => ram_block2a6.CLK0
clock0 => ram_block2a7.CLK0
clock0 => ram_block2a8.CLK0
clock0 => ram_block2a9.CLK0
clock0 => ram_block2a10.CLK0
clock0 => ram_block2a11.CLK0
clock0 => ram_block2a12.CLK0
clock0 => ram_block2a13.CLK0
clock0 => ram_block2a14.CLK0
clock0 => ram_block2a15.CLK0
clock0 => ram_block2a16.CLK0
clock0 => ram_block2a17.CLK0
clock0 => ram_block2a18.CLK0
clock0 => ram_block2a19.CLK0
clock0 => ram_block2a20.CLK0
clock0 => ram_block2a21.CLK0
clock0 => ram_block2a22.CLK0
clock0 => ram_block2a23.CLK0
clock0 => ram_block2a24.CLK0
clock0 => ram_block2a25.CLK0
clock0 => ram_block2a26.CLK0
clock0 => ram_block2a27.CLK0
clock0 => ram_block2a28.CLK0
clock0 => ram_block2a29.CLK0
clock0 => ram_block2a30.CLK0
clock0 => ram_block2a31.CLK0
clock0 => address_reg_a[0].CLK
clock0 => out_address_reg_a[0].CLK
clock1 => ram_block2a0.CLK1
clock1 => ram_block2a1.CLK1
clock1 => ram_block2a2.CLK1
clock1 => ram_block2a3.CLK1
clock1 => ram_block2a4.CLK1
clock1 => ram_block2a5.CLK1
clock1 => ram_block2a6.CLK1
clock1 => ram_block2a7.CLK1
clock1 => ram_block2a8.CLK1
clock1 => ram_block2a9.CLK1
clock1 => ram_block2a10.CLK1
clock1 => ram_block2a11.CLK1
clock1 => ram_block2a12.CLK1
clock1 => ram_block2a13.CLK1
clock1 => ram_block2a14.CLK1
clock1 => ram_block2a15.CLK1
clock1 => ram_block2a16.CLK1
clock1 => ram_block2a17.CLK1
clock1 => ram_block2a18.CLK1
clock1 => ram_block2a19.CLK1
clock1 => ram_block2a20.CLK1
clock1 => ram_block2a21.CLK1
clock1 => ram_block2a22.CLK1
clock1 => ram_block2a23.CLK1
clock1 => ram_block2a24.CLK1
clock1 => ram_block2a25.CLK1
clock1 => ram_block2a26.CLK1
clock1 => ram_block2a27.CLK1
clock1 => ram_block2a28.CLK1
clock1 => ram_block2a29.CLK1
clock1 => ram_block2a30.CLK1
clock1 => ram_block2a31.CLK1
clock1 => address_reg_b[0].CLK
clocken0 => decode_1oa:decode_a.enable
clocken0 => address_reg_a[0].ENA
clocken1 => ~NO_FANOUT~
data_a[0] => ram_block2a0.PORTADATAIN
data_a[0] => ram_block2a16.PORTADATAIN
data_a[1] => ram_block2a1.PORTADATAIN
data_a[1] => ram_block2a17.PORTADATAIN
data_a[2] => ram_block2a2.PORTADATAIN
data_a[2] => ram_block2a18.PORTADATAIN
data_a[3] => ram_block2a3.PORTADATAIN
data_a[3] => ram_block2a19.PORTADATAIN
data_a[4] => ram_block2a4.PORTADATAIN
data_a[4] => ram_block2a20.PORTADATAIN
data_a[5] => ram_block2a5.PORTADATAIN
data_a[5] => ram_block2a21.PORTADATAIN
data_a[6] => ram_block2a6.PORTADATAIN
data_a[6] => ram_block2a22.PORTADATAIN
data_a[7] => ram_block2a7.PORTADATAIN
data_a[7] => ram_block2a23.PORTADATAIN
data_a[8] => ram_block2a8.PORTADATAIN
data_a[8] => ram_block2a24.PORTADATAIN
data_a[9] => ram_block2a9.PORTADATAIN
data_a[9] => ram_block2a25.PORTADATAIN
data_a[10] => ram_block2a10.PORTADATAIN
data_a[10] => ram_block2a26.PORTADATAIN
data_a[11] => ram_block2a11.PORTADATAIN
data_a[11] => ram_block2a27.PORTADATAIN
data_a[12] => ram_block2a12.PORTADATAIN
data_a[12] => ram_block2a28.PORTADATAIN
data_a[13] => ram_block2a13.PORTADATAIN
data_a[13] => ram_block2a29.PORTADATAIN
data_a[14] => ram_block2a14.PORTADATAIN
data_a[14] => ram_block2a30.PORTADATAIN
data_a[15] => ram_block2a15.PORTADATAIN
data_a[15] => ram_block2a31.PORTADATAIN
data_b[0] => ram_block2a0.PORTBDATAIN
data_b[0] => ram_block2a16.PORTBDATAIN
data_b[1] => ram_block2a1.PORTBDATAIN
data_b[1] => ram_block2a17.PORTBDATAIN
data_b[2] => ram_block2a2.PORTBDATAIN
data_b[2] => ram_block2a18.PORTBDATAIN
data_b[3] => ram_block2a3.PORTBDATAIN
data_b[3] => ram_block2a19.PORTBDATAIN
data_b[4] => ram_block2a4.PORTBDATAIN
data_b[4] => ram_block2a20.PORTBDATAIN
data_b[5] => ram_block2a5.PORTBDATAIN
data_b[5] => ram_block2a21.PORTBDATAIN
data_b[6] => ram_block2a6.PORTBDATAIN
data_b[6] => ram_block2a22.PORTBDATAIN
data_b[7] => ram_block2a7.PORTBDATAIN
data_b[7] => ram_block2a23.PORTBDATAIN
data_b[8] => ram_block2a8.PORTBDATAIN
data_b[8] => ram_block2a24.PORTBDATAIN
data_b[9] => ram_block2a9.PORTBDATAIN
data_b[9] => ram_block2a25.PORTBDATAIN
data_b[10] => ram_block2a10.PORTBDATAIN
data_b[10] => ram_block2a26.PORTBDATAIN
data_b[11] => ram_block2a11.PORTBDATAIN
data_b[11] => ram_block2a27.PORTBDATAIN
data_b[12] => ram_block2a12.PORTBDATAIN
data_b[12] => ram_block2a28.PORTBDATAIN
data_b[13] => ram_block2a13.PORTBDATAIN
data_b[13] => ram_block2a29.PORTBDATAIN
data_b[14] => ram_block2a14.PORTBDATAIN
data_b[14] => ram_block2a30.PORTBDATAIN
data_b[15] => ram_block2a15.PORTBDATAIN
data_b[15] => ram_block2a31.PORTBDATAIN
q_a[0] <= mux_0kb:mux5.result[0]
q_a[1] <= mux_0kb:mux5.result[1]
q_a[2] <= mux_0kb:mux5.result[2]
q_a[3] <= mux_0kb:mux5.result[3]
q_a[4] <= mux_0kb:mux5.result[4]
q_a[5] <= mux_0kb:mux5.result[5]
q_a[6] <= mux_0kb:mux5.result[6]
q_a[7] <= mux_0kb:mux5.result[7]
q_a[8] <= mux_0kb:mux5.result[8]
q_a[9] <= mux_0kb:mux5.result[9]
q_a[10] <= mux_0kb:mux5.result[10]
q_a[11] <= mux_0kb:mux5.result[11]
q_a[12] <= mux_0kb:mux5.result[12]
q_a[13] <= mux_0kb:mux5.result[13]
q_a[14] <= mux_0kb:mux5.result[14]
q_a[15] <= mux_0kb:mux5.result[15]
q_b[0] <= mux_0kb:mux6.result[0]
q_b[1] <= mux_0kb:mux6.result[1]
q_b[2] <= mux_0kb:mux6.result[2]
q_b[3] <= mux_0kb:mux6.result[3]
q_b[4] <= mux_0kb:mux6.result[4]
q_b[5] <= mux_0kb:mux6.result[5]
q_b[6] <= mux_0kb:mux6.result[6]
q_b[7] <= mux_0kb:mux6.result[7]
q_b[8] <= mux_0kb:mux6.result[8]
q_b[9] <= mux_0kb:mux6.result[9]
q_b[10] <= mux_0kb:mux6.result[10]
q_b[11] <= mux_0kb:mux6.result[11]
q_b[12] <= mux_0kb:mux6.result[12]
q_b[13] <= mux_0kb:mux6.result[13]
q_b[14] <= mux_0kb:mux6.result[14]
q_b[15] <= mux_0kb:mux6.result[15]
wren_a => decode_1oa:decode3.enable
wren_b => decode_1oa:decode4.enable


|sram|altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|decode_1oa:decode3
data[0] => eq_node[1].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|sram|altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|decode_1oa:decode4
data[0] => eq_node[1].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|sram|altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|decode_1oa:decode_a
data[0] => eq_node[1].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|sram|altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|decode_1oa:decode_b
data[0] => eq_node[1].IN0
enable => eq_node[1].IN1
enable => eq_node[0].IN1
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|sram|altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|mux_0kb:mux5
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= result_node[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= result_node[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= result_node[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= result_node[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= result_node[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= result_node[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= result_node[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= result_node[15].DB_MAX_OUTPUT_PORT_TYPE


|sram|altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|mux_0kb:mux6
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= result_node[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= result_node[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= result_node[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= result_node[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= result_node[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= result_node[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= result_node[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= result_node[15].DB_MAX_OUTPUT_PORT_TYPE