sram.hier_info

基于altera ep2c8双口RAM

address_a[12] => decode_1oa:decode_a.data[0]
address_b[0] => ram_block2a0.PORTBADDR
address_b[0] => ram_block2a1.PORTBADDR
address_b[0] => ram_block2a2.PORTBADDR
address_b[0] => ram_block2a3.PORTBADDR
address_b[0] => ram_block2a4.PORTBADDR
address_b[0] => ram_block2a5.PORTBADDR
address_b[0] => ram_block2a6.PORTBADDR
address_b[0] => ram_block2a7.PORTBADDR
address_b[0] => ram_block2a8.PORTBADDR
address_b[0] => ram_block2a9.PORTBADDR
address_b[0] => ram_block2a10.PORTBADDR
address_b[0] => ram_block2a11.PORTBADDR
address_b[0] => ram_block2a12.PORTBADDR
address_b[0] => ram_block2a13.PORTBADDR
address_b[0] => ram_block2a14.PORTBADDR
address_b[0] => ram_block2a15.PORTBADDR
address_b[0] => ram_block2a16.PORTBADDR
address_b[0] => ram_block2a17.PORTBADDR
address_b[0] => ram_block2a18.PORTBADDR
address_b[0] => ram_block2a19.PORTBADDR
address_b[0] => ram_block2a20.PORTBADDR
address_b[0] => ram_block2a21.PORTBADDR
address_b[0] => ram_block2a22.PORTBADDR
address_b[0] => ram_block2a23.PORTBADDR
address_b[0] => ram_block2a24.PORTBADDR
address_b[0] => ram_block2a25.PORTBADDR
address_b[0] => ram_block2a26.PORTBADDR
address_b[0] => ram_block2a27.PORTBADDR
address_b[0] => ram_block2a28.PORTBADDR
address_b[0] => ram_block2a29.PORTBADDR
address_b[0] => ram_block2a30.PORTBADDR
address_b[0] => ram_block2a31.PORTBADDR
address_b[1] => ram_block2a0.PORTBADDR1
address_b[1] => ram_block2a1.PORTBADDR1
address_b[1] => ram_block2a2.PORTBADDR1
address_b[1] => ram_block2a3.PORTBADDR1
address_b[1] => ram_block2a4.PORTBADDR1
address_b[1] => ram_block2a5.PORTBADDR1
address_b[1] => ram_block2a6.PORTBADDR1
address_b[1] => ram_block2a7.PORTBADDR1
address_b[1] => ram_block2a8.PORTBADDR1
address_b[1] => ram_block2a9.PORTBADDR1
address_b[1] => ram_block2a10.PORTBADDR1
address_b[1] => ram_block2a11.PORTBADDR1
address_b[1] => ram_block2a12.PORTBADDR1
address_b[1] => ram_block2a13.PORTBADDR1
address_b[1] => ram_block2a14.PORTBADDR1
address_b[1] => ram_block2a15.PORTBADDR1
address_b[1] => ram_block2a16.PORTBADDR1
address_b[1] => ram_block2a17.PORTBADDR1
address_b[1] => ram_block2a18.PORTBADDR1
address_b[1] => ram_block2a19.PORTBADDR1
address_b[1] => ram_block2a20.PORTBADDR1
address_b[1] => ram_block2a21.PORTBADDR1
address_b[1] => ram_block2a22.PORTBADDR1
address_b[1] => ram_block2a23.PORTBADDR1
address_b[1] => ram_block2a24.PORTBADDR1
address_b[1] => ram_block2a25.PORTBADDR1
address_b[1] => ram_block2a26.PORTBADDR1
address_b[1] => ram_block2a27.PORTBADDR1
address_b[1] => ram_block2a28.PORTBADDR1
address_b[1] => ram_block2a29.PORTBADDR1
address_b[1] => ram_block2a30.PORTBADDR1
address_b[1] => ram_block2a31.PORTBADDR1
address_b[2] => ram_block2a0.PORTBADDR2
address_b[2] => ram_block2a1.PORTBADDR2
address_b[2] => ram_block2a2.PORTBADDR2
address_b[2] => ram_block2a3.PORTBADDR2
address_b[2] => ram_block2a4.PORTBADDR2
address_b[2] => ram_block2a5.PORTBADDR2
address_b[2] => ram_block2a6.PORTBADDR2
address_b[2] => ram_block2a7.PORTBADDR2
address_b[2] => ram_block2a8.PORTBADDR2
address_b[2] => ram_block2a9.PORTBADDR2
address_b[2] => ram_block2a10.PORTBADDR2
address_b[2] => ram_block2a11.PORTBADDR2
address_b[2] => ram_block2a12.PORTBADDR2
address_b[2] => ram_block2a13.PORTBADDR2
address_b[2] => ram_block2a14.PORTBADDR2
address_b[2] => ram_block2a15.PORTBADDR2
address_b[2] => ram_block2a16.PORTBADDR2
address_b[2] => ram_block2a17.PORTBADDR2
address_b[2] => ram_block2a18.PORTBADDR2
address_b[2] => ram_block2a19.PORTBADDR2
address_b[2] => ram_block2a20.PORTBADDR2
address_b[2] => ram_block2a21.PORTBADDR2
address_b[2] => ram_block2a22.PORTBADDR2
address_b[2] => ram_block2a23.PORTBADDR2
address_b[2] => ram_block2a24.PORTBADDR2
address_b[2] => ram_block2a25.PORTBADDR2
address_b[2] => ram_block2a26.PORTBADDR2
address_b[2] => ram_block2a27.PORTBADDR2
address_b[2] => ram_block2a28.PORTBADDR2
address_b[2] => ram_block2a29.PORTBADDR2
address_b[2] => ram_block2a30.PORTBADDR2
address_b[2] => ram_block2a31.PORTBADDR2
address_b[3] => ram_block2a0.PORTBADDR3
address_b[3] => ram_block2a1.PORTBADDR3
address_b[3] => ram_block2a2.PORTBADDR3
address_b[3] => ram_block2a3.PORTBADDR3
address_b[3] => ram_block2a4.PORTBADDR3
address_b[3] => ram_block2a5.PORTBADDR3
address_b[3] => ram_block2a6.PORTBADDR3
address_b[3] => ram_block2a7.PORTBADDR3
address_b[3] => ram_block2a8.PORTBADDR3
address_b[3] => ram_block2a9.PORTBADDR3
address_b[3] => ram_block2a10.PORTBADDR3
address_b[3] => ram_block2a11.PORTBADDR3
address_b[3] => ram_block2a12.PORTBADDR3
address_b[3] => ram_block2a13.PORTBADDR3
address_b[3] => ram_block2a14.PORTBADDR3
address_b[3] => ram_block2a15.PORTBADDR3
address_b[3] => ram_block2a16.PORTBADDR3
address_b[3] => ram_block2a17.PORTBADDR3
address_b[3] => ram_block2a18.PORTBADDR3
address_b[3] => ram_block2a19.PORTBADDR3
address_b[3] => ram_block2a20.PORTBADDR3
address_b[3] => ram_block2a21.PORTBADDR3
address_b[3] => ram_block2a22.PORTBADDR3
address_b[3] => ram_block2a23.PORTBADDR3
address_b[3] => ram_block2a24.PORTBADDR3
address_b[3] => ram_block2a25.PORTBADDR3
address_b[3] => ram_block2a26.PORTBADDR3
address_b[3] => ram_block2a27.PORTBADDR3
address_b[3] => ram_block2a28.PORTBADDR3
address_b[3] => ram_block2a29.PORTBADDR3
address_b[3] => ram_block2a30.PORTBADDR3
address_b[3] => ram_block2a31.PORTBADDR3
address_b[4] => ram_block2a0.PORTBADDR4
address_b[4] => ram_block2a1.PORTBADDR4
address_b[4] => ram_block2a2.PORTBADDR4
address_b[4] => ram_block2a3.PORTBADDR4
address_b[4] => ram_block2a4.PORTBADDR4
address_b[4] => ram_block2a5.PORTBADDR4
address_b[4] => ram_block2a6.PORTBADDR4
address_b[4] => ram_block2a7.PORTBADDR4
address_b[4] => ram_block2a8.PORTBADDR4
address_b[4] => ram_block2a9.PORTBADDR4
address_b[4] => ram_block2a10.PORTBADDR4
address_b[4] => ram_block2a11.PORTBADDR4
address_b[4] => ram_block2a12.PORTBADDR4
address_b[4] => ram_block2a13.PORTBADDR4
address_b[4] => ram_block2a14.PORTBADDR4
address_b[4] => ram_block2a15.PORTBADDR4
address_b[4] => ram_block2a16.PORTBADDR4
address_b[4] => ram_block2a17.PORTBADDR4
address_b[4] => ram_block2a18.PORTBADDR4
address_b[4] => ram_block2a19.PORTBADDR4
address_b[4] => ram_block2a20.PORTBADDR4
address_b[4] => ram_block2a21.PORTBADDR4
address_b[4] => ram_block2a22.PORTBADDR4
address_b[4] => ram_block2a23.PORTBADDR4
address_b[4] => ram_block2a24.PORTBADDR4
address_b[4] => ram_block2a25.PORTBADDR4
address_b[4] => ram_block2a26.PORTBADDR4
address_b[4] => ram_block2a27.PORTBADDR4
address_b[4] => ram_block2a28.PORTBADDR4
address_b[4] => ram_block2a29.PORTBADDR4
address_b[4] => ram_block2a30.PORTBADDR4
address_b[4] => ram_block2a31.PORTBADDR4
address_b[5] => ram_block2a0.PORTBADDR5
address_b[5] => ram_block2a1.PORTBADDR5
address_b[5] => ram_block2a2.PORTBADDR5
address_b[5] => ram_block2a3.PORTBADDR5
address_b[5] => ram_block2a4.PORTBADDR5
address_b[5] => ram_block2a5.PORTBADDR5
address_b[5] => ram_block2a6.PORTBADDR5
address_b[5] => ram_block2a7.PORTBADDR5
address_b[5] => ram_block2a8.PORTBADDR5
address_b[5] => ram_block2a9.PORTBADDR5
address_b[5] => ram_block2a10.PORTBADDR5
address_b[5] => ram_block2a11.PORTBADDR5
address_b[5] => ram_block2a12.PORTBADDR5
address_b[5] => ram_block2a13.PORTBADDR5
address_b[5] => ram_block2a14.PORTBADDR5
address_b[5] => ram_block2a15.PORTBADDR5
address_b[5] => ram_block2a16.PORTBADDR5
address_b[5] => ram_block2a17.PORTBADDR5
address_b[5] => ram_block2a18.PORTBADDR5
address_b[5] => ram_block2a19.PORTBADDR5
address_b[5] => ram_block2a20.PORTBADDR5
address_b[5] => ram_block2a21.PORTBADDR5
address_b[5] => ram_block2a22.PORTBADDR5
address_b[5] => ram_block2a23.PORTBADDR5
address_b[5] => ram_block2a24.PORTBADDR5
address_b[5] => ram_block2a25.PORTBADDR5
address_b[5] => ram_block2a26.PORTBADDR5
address_b[5] => ram_block2a27.PORTBADDR5
address_b[5] => ram_block2a28.PORTBADDR5
address_b[5] => ram_block2a29.PORTBADDR5
address_b[5] => ram_block2a30.PORTBADDR5
address_b[5] => ram_block2a31.PORTBADDR5
address_b[6] => ram_block2a0.PORTBADDR6
address_b[6] => ram_block2a1.PORTBADDR6
address_b[6] => ram_block2a2.PORTBADDR6
address_b[6] => ram_block2a3.PORTBADDR6
address_b[6] => ram_block2a4.PORTBADDR6
address_b[6] => ram_block2a5.PORTBADDR6
address_b[6] => ram_block2a6.PORTBADDR6
address_b[6] => ram_block2a7.PORTBADDR6
address_b[6] => ram_block2a8.PORTBADDR6
address_b[6] => ram_block2a9.PORTBADDR6
address_b[6] => ram_block2a10.PORTBADDR6
address_b[6] => ram_block2a11.PORTBADDR6
address_b[6] => ram_block2a12.PORTBADDR6
address_b[6] => ram_block2a13.PORTBADDR6
address_b[6] => ram_block2a14.PORTBADDR6
address_b[6] => ram_block2a15.PORTBADDR6
address_b[6] => ram_block2a16.PORTBADDR6
address_b[6] => ram_block2a17.PORTBADDR6
address_b[6] => ram_block2a18.PORTBADDR6
address_b[6] => ram_block2a19.PORTBADDR6
address_b[6] => ram_block2a20.PORTBADDR6
address_b[6] => ram_block2a21.PORTBADDR6
address_b[6] => ram_block2a22.PORTBADDR6
address_b[6] => ram_block2a23.PORTBADDR6
address_b[6] => ram_block2a24.PORTBADDR6
address_b[6] => ram_block2a25.PORTBADDR6
address_b[6] => ram_block2a26.PORTBADDR6
address_b[6] => ram_block2a27.PORTBADDR6
address_b[6] => ram_block2a28.PORTBADDR6
address_b[6] => ram_block2a29.PORTBADDR6
address_b[6] => ram_block2a30.PORTBADDR6
address_b[6] => ram_block2a31.PORTBADDR6
address_b[7] => ram_block2a0.PORTBADDR7
address_b[7] => ram_block2a1.PORTBADDR7
address_b[7] => ram_block2a2.PORTBADDR7
address_b[7] => ram_block2a3.PORTBADDR7
address_b[7] => ram_block2a4.PORTBADDR7
address_b[7] => ram_block2a5.PORTBADDR7
address_b[7] => ram_block2a6.PORTBADDR7
address_b[7] => ram_block2a7.PORTBADDR7
address_b[7] => ram_block2a8.PORTBADDR7
address_b[7] => ram_block2a9.PORTBADDR7
address_b[7] => ram_block2a10.PORTBADDR7
address_b[7] => ram_block2a11.PORTBADDR7
address_b[7] => ram_block2a12.PORTBADDR7
address_b[7] => ram_block2a13.PORTBADDR7
address_b[7] => ram_block2a14.PORTBADDR7
address_b[7] => ram_block2a15.PORTBADDR7
address_b[7] => ram_block2a16.PORTBADDR7
address_b[7] => ram_block2a17.PORTBADDR7
address_b[7] => ram_block2a18.PORTBADDR7
address_b[7] => ram_block2a19.PORTBADDR7
address_b[7] => ram_block2a20.PORTBADDR7
address_b[7] => ram_block2a21.PORTBADDR7
address_b[7] => ram_block2a22.PORTBADDR7
address_b[7] => ram_block2a23.PORTBADDR7
address_b[7] => ram_block2a24.PORTBADDR7
address_b[7] => ram_block2a25.PORTBADDR7
address_b[7] => ram_block2a26.PORTBADDR7
address_b[7] => ram_block2a27.PORTBADDR7
address_b[7] => ram_block2a28.PORTBADDR7
address_b[7] => ram_block2a29.PORTBADDR7
address_b[7] => ram_block2a30.PORTBADDR7
address_b[7] => ram_block2a31.PORTBADDR7
address_b[8] => ram_block2a0.PORTBADDR8
address_b[8] => ram_block2a1.PORTBADDR8
address_b[8] => ram_block2a2.PORTBADDR8
address_b[8] => ram_block2a3.PORTBADDR8
address_b[8] => ram_block2a4.PORTBADDR8
address_b[8] => ram_block2a5.PORTBADDR8
address_b[8] => ram_block2a6.PORTBADDR8
address_b[8] => ram_block2a7.PORTBADDR8
address_b[8] => ram_block2a8.PORTBADDR8
address_b[8] => ram_block2a9.PORTBADDR8
address_b[8] => ram_block2a10.PORTBADDR8
address_b[8] => ram_block2a11.PORTBADDR8
address_b[8] => ram_block2a12.PORTBADDR8
address_b[8] => ram_block2a13.PORTBADDR8
address_b[8] => ram_block2a14.PORTBADDR8
address_b[8] => ram_block2a15.PORTBADDR8
address_b[8] => ram_block2a16.PORTBADDR8
address_b[8] => ram_block2a17.PORTBADDR8
address_b[8] => ram_block2a18.PORTBADDR8
address_b[8] => ram_block2a19.PORTBADDR8
address_b[8] => ram_block2a20.PORTBADDR8
address_b[8] => ram_block2a21.PORTBADDR8
address_b[8] => ram_block2a22.PORTBADDR8
address_b[8] => ram_block2a23.PORTBADDR8
address_b[8] => ram_block2a24.PORTBADDR8
address_b[8] => ram_block2a25.PORTBADDR8
address_b[8] => ram_block2a26.PORTBADDR8
address_b[8] => ram_block2a27.PORTBADDR8
address_b[8] => ram_block2a28.PORTBADDR8
address_b[8] => ram_block2a29.PORTBADDR8
address_b[8] => ram_block2a30.PORTBADDR8
address_b[8] => ram_block2a31.PORTBADDR8
address_b[9] => ram_block2a0.PORTBADDR9
address_b[9] => ram_block2a1.PORTBADDR9
address_b[9] => ram_block2a2.PORTBADDR9
address_b[9] => ram_block2a3.PORTBADDR9
address_b[9] => ram_block2a4.PORTBADDR9
address_b[9] => ram_block2a5.PORTBADDR9
address_b[9] => ram_block2a6.PORTBADDR9
address_b[9] => ram_block2a7.PORTBADDR9
address_b[9] => ram_block2a8.PORTBADDR9
address_b[9] => ram_block2a9.PORTBADDR9
address_b[9] => ram_block2a10.PORTBADDR9
address_b[9] => ram_block2a11.PORTBADDR9
address_b[9] => ram_block2a12.PORTBADDR9
address_b[9] => ram_block2a13.PORTBADDR9
address_b[9] => ram_block2a14.PORTBADDR9
address_b[9] => ram_block2a15.PORTBADDR9
address_b[9] => ram_block2a16.PORTBADDR9
address_b[9] => ram_block2a17.PORTBADDR9
address_b[9] => ram_block2a18.PORTBADDR9
address_b[9] => ram_block2a19.PORTBADDR9
address_b[9] => ram_block2a20.PORTBADDR9
address_b[9] => ram_block2a21.PORTBADDR9
address_b[9] => ram_block2a22.PORTBADDR9
address_b[9] => ram_block2a23.PORTBADDR9
address_b[9] => ram_block2a24.PORTBADDR9
address_b[9] => ram_block2a25.PORTBADDR9