sram.tan.rpt

基于altera ep2c8双口RAM

+------------------------------+-------+---------------+------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 7.461 ns                                       ; wraddress[5]                                                                                                               ; altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a0~portb_address_reg5 ; --         ; wrclock  ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 13.612 ns                                      ; altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a6                    ; q[6]                                                                                                                       ; rdclock    ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.074 ns                                      ; rdaddress[12]                                                                                                              ; altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|address_reg_a[0]                ; --         ; rdclock  ; 0            ;
; Clock Setup: 'wrclock'       ; N/A   ; None          ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a15~portb_datain_reg0 ; altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a15~portb_memory_reg0 ; wrclock    ; wrclock  ; 0            ;
; Clock Setup: 'rdclock'       ; N/A   ; None          ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7~porta_address_reg3 ; altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|ram_block2a7                    ; rdclock    ; rdclock  ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                                                                            ;                                                                                                                            ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2C8T144C8        ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; rdclock         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;