sram.map.rpt

基于altera ep2c8双口RAM

+---------------------------------+--------------------+------+-------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Source assignments for altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1 ;
+---------------------------------+--------------------+------+-----------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                  ;
+---------------------------------+--------------------+------+-----------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                   ;
+---------------------------------+--------------------+------+-----------------------------------------------------+


+------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: altsyncram:altsyncram_component ;
+------------------------------------+----------------------+------------------+
; Parameter Name                     ; Value                ; Type             ;
+------------------------------------+----------------------+------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped          ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY       ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY     ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE     ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE   ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped          ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped          ;
; WIDTH_A                            ; 16                   ; Signed Integer   ;
; WIDTHAD_A                          ; 13                   ; Signed Integer   ;
; NUMWORDS_A                         ; 8192                 ; Signed Integer   ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped          ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped          ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped          ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped          ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped          ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped          ;
; WIDTH_B                            ; 16                   ; Signed Integer   ;
; WIDTHAD_B                          ; 13                   ; Signed Integer   ;
; NUMWORDS_B                         ; 8192                 ; Signed Integer   ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped          ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped          ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped          ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped          ;
; OUTDATA_REG_B                      ; CLOCK1               ; Untyped          ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped          ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped          ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped          ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped          ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped          ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped          ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped          ;
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer   ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped          ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped          ;
; BYTE_SIZE                          ; 8                    ; Untyped          ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped          ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped          ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped          ;
; INIT_FILE                          ; UNUSED               ; Untyped          ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped          ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped          ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped          ;
; CLOCK_ENABLE_INPUT_B               ; BYPASS               ; Untyped          ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS               ; Untyped          ;
; CLOCK_ENABLE_OUTPUT_B              ; BYPASS               ; Untyped          ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped          ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped          ;
; ENABLE_ECC                         ; FALSE                ; Untyped          ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped          ;
; CBXI_PARAMETER                     ; altsyncram_pfn1      ; Untyped          ;
+------------------------------------+----------------------+------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Apr 14 08:31:37 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sram -c sram
Warning: Using design file sram.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: sram-SYN
    Info: Found entity 1: sram
Info: Elaborating entity "sram" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pfn1.tdf
    Info: Found entity 1: altsyncram_pfn1
Info: Elaborating entity "altsyncram_pfn1" for hierarchy "altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_d7t1.tdf
    Info: Found entity 1: altsyncram_d7t1
Info: Elaborating entity "altsyncram_d7t1" for hierarchy "altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1"
Warning: Variable or input pin "clocken1" is defined but never used
Info: Found 1 design units, including 1 entities, in source file db/decode_1oa.tdf
    Info: Found entity 1: decode_1oa
Info: Elaborating entity "decode_1oa" for hierarchy "altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|decode_1oa:decode3"
Info: Elaborating entity "decode_1oa" for hierarchy "altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|decode_1oa:decode_b"
Info: Found 1 design units, including 1 entities, in source file db/mux_0kb.tdf
    Info: Found entity 1: mux_0kb
Info: Elaborating entity "mux_0kb" for hierarchy "altsyncram:altsyncram_component|altsyncram_pfn1:auto_generated|altsyncram_d7t1:altsyncram1|mux_0kb:mux5"
Info: Implemented 116 device resources after synthesis - the final resource count might be different
    Info: Implemented 46 input pins
    Info: Implemented 16 output pins
    Info: Implemented 22 logic cells
    Info: Implemented 32 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Allocated 164 megabytes of memory during processing
    Info: Processing ended: Tue Apr 14 08:31:44 2009
    Info: Elapsed time: 00:00:07