sram.fit.rpt

基于altera ep2c8双口RAM

; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/毕业设计/毕业设计软件/FPGA/ram/sram.pin.


+--------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                            ;
+---------------------------------------------+----------------------------+
; Resource                                    ; Usage                      ;
+---------------------------------------------+----------------------------+
; Total logic elements                        ; 21 / 8,256 ( < 1 % )       ;
;     -- Combinational with no register       ; 19                         ;
;     -- Register only                        ; 1                          ;
;     -- Combinational with a register        ; 1                          ;
;                                             ;                            ;
; Logic element usage by number of LUT inputs ;                            ;
;     -- 4 input functions                    ; 0                          ;
;     -- 3 input functions                    ; 16                         ;
;     -- <=2 input functions                  ; 4                          ;
;     -- Register only                        ; 1                          ;
;                                             ;                            ;
; Logic elements by mode                      ;                            ;
;     -- normal mode                          ; 20                         ;
;     -- arithmetic mode                      ; 0                          ;
;                                             ;                            ;
; Total registers*                            ; 2 / 8,487 ( < 1 % )        ;
;     -- Dedicated logic registers            ; 2 / 8,256 ( < 1 % )        ;
;     -- I/O registers                        ; 0 / 231 ( 0 % )            ;
;                                             ;                            ;
; Total LABs:  partially or completely used   ; 3 / 516 ( < 1 % )          ;
; User inserted logic elements                ; 0                          ;
; Virtual pins                                ; 0                          ;
; I/O pins                                    ; 62 / 85 ( 73 % )           ;
;     -- Clock pins                           ; 3 / 4 ( 75 % )             ;
; Global signals                              ; 2                          ;
; M4Ks                                        ; 32 / 36 ( 89 % )           ;
; Total memory bits                           ; 131,072 / 165,888 ( 79 % ) ;
; Total RAM block bits                        ; 147,456 / 165,888 ( 89 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 36 ( 0 % )             ;
; PLLs                                        ; 0 / 2 ( 0 % )              ;
; Global clocks                               ; 2 / 8 ( 25 % )             ;
; Average interconnect usage                  ; 2%                         ;
; Peak interconnect usage                     ; 4%                         ;
; Maximum fan-out node                        ; wraddress[12]              ;
; Maximum fan-out                             ; 34                         ;
; Highest non-global fan-out signal           ; wraddress[12]              ;
; Highest non-global fan-out                  ; 34                         ;
; Total fan-out                               ; 1039                       ;
; Average fan-out                             ; 8.59                       ;
+---------------------------------------------+----------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                          ;
+---------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name          ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+---------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+