_primary.vhd

its a Fifo BASED design i also Interface DAC2904

library verilog;
use verilog.vl_types.all;
entity fifo_generator_v3_2_bhv_ver_preload0 is
    generic(
        c_dout_rst_val  : string  := "";
        c_dout_width    : integer := 8;
        c_has_rst       : integer := 0;
        c_uservalid_low : integer := 0;
        c_userunderflow_low: integer := 0
    );
    port(
        rd_clk          : in     vl_logic;
        rd_rst          : in     vl_logic;
        rd_en           : in     vl_logic;
        fifoempty       : in     vl_logic;
        fifodata        : in     vl_logic_vector;
        userdata        : out    vl_logic_vector;
        uservalid       : out    vl_logic;
        userunderflow   : out    vl_logic;
        userempty       : out    vl_logic;
        useralmostempty : out    vl_logic;
        ramvalid        : out    vl_logic;
        fiforden        : out    vl_logic
    );
end fifo_generator_v3_2_bhv_ver_preload0;