_primary.vhd

its a Fifo BASED design i also Interface DAC2904

library verilog;
use verilog.vl_types.all;
entity fifo_generator_v3_2_bhv_ver_ss is
    generic(
        c_common_clock  : integer := 0;
        c_count_type    : integer := 0;
        c_data_count_width: integer := 2;
        c_default_value : string  := "";
        c_din_width     : integer := 8;
        c_dout_rst_val  : string  := "";
        c_dout_width    : integer := 8;
        c_enable_rlocs  : integer := 0;
        c_family        : string  := "virtex2";
        c_has_almost_empty: integer := 0;
        c_has_almost_full: integer := 0;
        c_has_backup    : integer := 0;
        c_has_data_count: integer := 0;
        c_has_meminit_file: integer := 0;
        c_has_overflow  : integer := 0;
        c_has_rd_data_count: integer := 0;
        c_has_rd_rst    : integer := 0;
        c_has_rst       : integer := 0;
        c_has_srst      : integer := 0;
        c_has_underflow : integer := 0;
        c_has_valid     : integer := 0;
        c_has_wr_ack    : integer := 0;
        c_has_wr_data_count: integer := 0;
        c_has_wr_rst    : integer := 0;
        c_implementation_type: integer := 0;
        c_init_wr_pntr_val: integer := 0;
        c_memory_type   : integer := 1;
        c_mif_file_name : string  := "";
        c_optimization_mode: integer := 0;
        c_overflow_low  : integer := 0;
        c_preload_latency: integer := 1;
        c_preload_regs  : integer := 0;
        c_prog_empty_thresh_assert_val: integer := 0;
        c_prog_empty_thresh_negate_val: integer := 0;
        c_prog_empty_type: integer := 0;
        c_prog_full_thresh_assert_val: integer := 0;
        c_prog_full_thresh_negate_val: integer := 0;
        c_prog_full_type: integer := 0;
        c_rd_data_count_width: integer := 2;
        c_rd_depth      : integer := 256;
        c_rd_pntr_width : integer := 8;
        c_underflow_low : integer := 0;
        c_valid_low     : integer := 0;
        c_wr_ack_low    : integer := 0;
        c_wr_data_count_width: integer := 2;
        c_wr_depth      : integer := 256;
        c_wr_pntr_width : integer := 8;
        c_wr_response_latency: integer := 1;
        c_has_fast_fifo : integer := 0
    );
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        srst            : in     vl_logic;
        din             : in     vl_logic_vector;
        wr_en           : in     vl_logic;
        rd_en           : in     vl_logic;
        prog_full_thresh: in     vl_logic_vector;
        prog_full_thresh_assert: in     vl_logic_vector;
        prog_full_thresh_negate: in     vl_logic_vector;
        prog_empty_thresh: in     vl_logic_vector;
        prog_empty_thresh_assert: in     vl_logic_vector;
        prog_empty_thresh_negate: in     vl_logic_vector;
        dout            : out    vl_logic_vector;
        full            : out    vl_logic;
        almost_full     : out    vl_logic;
        wr_ack          : out    vl_logic;
        overflow        : out    vl_logic;
        empty           : out    vl_logic;
        almost_empty    : out    vl_logic;
        valid           : out    vl_logic;
        underflow       : out    vl_logic;
        data_count      : out    vl_logic_vector;
        prog_full       : out    vl_logic;
        prog_empty      : out    vl_logic
    );
end fifo_generator_v3_2_bhv_ver_ss;