coregen.cgp

来自「its a Fifo BASED design i also Interfac」· CGP 代码 · 共 21 行

# Date: Fri Jan 16 07:27:55 2009
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = Verilog
SET device = xc3s1400an
SET devicefamily = spartan3a
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fg676
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = False
SET workingdirectory = D:\Projects\Transceiver\Code\FIFO\core\FIFO\coregen\tmp