vga_colors.map.rpt

通过vga通讯控制显示器显示七彩条文

+---------------------------------------------+----------+
; Resource                                    ; Usage    ;
+---------------------------------------------+----------+
; Total logic elements                        ; 74       ;
;     -- Combinational with no register       ; 43       ;
;     -- Register only                        ; 19       ;
;     -- Combinational with a register        ; 12       ;
;                                             ;          ;
; Logic element usage by number of LUT inputs ;          ;
;     -- 4 input functions                    ; 26       ;
;     -- 3 input functions                    ; 3        ;
;     -- 2 input functions                    ; 24       ;
;     -- 1 input functions                    ; 2        ;
;     -- 0 input functions                    ; 0        ;
;                                             ;          ;
; Logic elements by mode                      ;          ;
;     -- normal mode                          ; 52       ;
;     -- arithmetic mode                      ; 22       ;
;     -- qfbk mode                            ; 0        ;
;     -- register cascade mode                ; 0        ;
;     -- synchronous clear/load mode          ; 0        ;
;     -- asynchronous clear/load mode         ; 0        ;
;                                             ;          ;
; Total registers                             ; 31       ;
; Total logic cells in carry chains           ; 24       ;
; I/O pins                                    ; 7        ;
; Maximum fan-out node                        ; clk_div2 ;
; Maximum fan-out                             ; 31       ;
; Total fan-out                               ; 233      ;
; Average fan-out                             ; 2.88     ;
+---------------------------------------------+----------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                          ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name        ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+--------------+
; |VgaColors                 ; 74 (1)      ; 31           ; 0           ; 7    ; 0            ; 43 (0)       ; 19 (0)            ; 12 (1)           ; 24 (0)          ; 0 (0)      ; |VgaColors                 ; work         ;
;    |VgaSync:vgaSync|       ; 73 (73)     ; 30           ; 0           ; 0    ; 0            ; 43 (43)      ; 19 (19)           ; 11 (11)          ; 24 (24)         ; 0 (0)      ; |VgaColors|VgaSync:vgaSync ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 31    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 15    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; VgaSync:vgaSync|signal                 ; 2       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
; 5:1                ; 3 bits    ; 9 LEs         ; 3 LEs                ; 6 LEs                  ; Yes        ; |VgaColors|VgaSync:vgaSync|redOut  ;
; 5:1                ; 12 bits   ; 36 LEs        ; 12 LEs               ; 24 LEs                 ; Yes        ; |VgaColors|VgaSync:vgaSync|line[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+


+--------------------------------------------------------------+
; Parameter Settings for User Entity Instance: VgaSync:vgaSync ;
+----------------+-------+-------------------------------------+
; Parameter Name ; Value ; Type                                ;
+----------------+-------+-------------------------------------+
; H_PIXELS       ; 640   ; Signed Integer                      ;
; H_FRONT        ; 16    ; Signed Integer                      ;
; H_SYNC         ; 96    ; Signed Integer                      ;
; H_BACK         ; 48    ; Signed Integer                      ;
; H_SYNC_VALUE   ; 0     ; Unsigned Binary                     ;
; V_LINES        ; 480   ; Signed Integer                      ;
; V_FRONT        ; 10    ; Signed Integer                      ;
; V_SYNC         ; 2     ; Signed Integer                      ;
; V_BACK         ; 33    ; Signed Integer                      ;
; V_SYNC_VALUE   ; 0     ; Unsigned Binary                     ;
+----------------+-------+-------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Mon Mar 09 20:27:27 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_colors -c vga_colors
Warning: Partition name "Top" is reserved -- specify a different name
Info: Found 1 design units, including 1 entities, in source file vga_colors.v
    Info: Found entity 1: VgaColors
Info: Found 1 design units, including 1 entities, in source file vga_sync.v
    Info: Found entity 1: VgaSync
Info: Elaborating entity "VgaColors" for the top level hierarchy
Info: Elaborating entity "VgaSync" for hierarchy "VgaSync:vgaSync"
Warning: Port "line" on the entity instantiation of "vgaSync" is connected to a signal of width 1. The formal width of the signal in the module is 12.  Extra bits will be left dangling without any fanout logic.
Info: Implemented 81 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 5 output pins
    Info: Implemented 74 logic cells
Info: Generated suppressed messages file F:/fpga/vga_可用程序/vga_colors/vga_colors.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Allocated 135 megabytes of memory during processing
    Info: Processing ended: Mon Mar 09 20:27:33 2009
    Info: Elapsed time: 00:00:06


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in F:/fpga/vga_可用程序/vga_colors/vga_colors.map.smsg.