vga_colors.fit.qmsg

通过vga通讯控制显示器显示七彩条文

{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.583 ns register register " "Info: Estimated most critical path is register to register delay of 5.583 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VgaSync:vgaSync\|pixel\[0\] 1 REG LAB_X47_Y12 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X47_Y12; Fanout = 3; REG Node = 'VgaSync:vgaSync\|pixel\[0\]'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VgaSync:vgaSync|pixel[0] } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 163 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.114 ns) 0.782 ns VgaSync:vgaSync\|Equal0~134 2 COMB LAB_X47_Y12 1 " "Info: 2: + IC(0.668 ns) + CELL(0.114 ns) = 0.782 ns; Loc. = LAB_X47_Y12; Fanout = 1; COMB Node = 'VgaSync:vgaSync\|Equal0~134'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.782 ns" { VgaSync:vgaSync|pixel[0] VgaSync:vgaSync|Equal0~134 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 165 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.116 ns) + CELL(0.590 ns) 1.488 ns VgaSync:vgaSync\|Equal0~135 3 COMB LAB_X47_Y12 2 " "Info: 3: + IC(0.116 ns) + CELL(0.590 ns) = 1.488 ns; Loc. = LAB_X47_Y12; Fanout = 2; COMB Node = 'VgaSync:vgaSync\|Equal0~135'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.706 ns" { VgaSync:vgaSync|Equal0~134 VgaSync:vgaSync|Equal0~135 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 165 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.116 ns) + CELL(0.590 ns) 2.194 ns VgaSync:vgaSync\|Equal4~100 4 COMB LAB_X47_Y12 8 " "Info: 4: + IC(0.116 ns) + CELL(0.590 ns) = 2.194 ns; Loc. = LAB_X47_Y12; Fanout = 8; COMB Node = 'VgaSync:vgaSync\|Equal4~100'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.706 ns" { VgaSync:vgaSync|Equal0~135 VgaSync:vgaSync|Equal4~100 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 187 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.676 ns) + CELL(0.590 ns) 3.460 ns VgaSync:vgaSync\|vSync~136 5 COMB LAB_X51_Y12 2 " "Info: 5: + IC(0.676 ns) + CELL(0.590 ns) = 3.460 ns; Loc. = LAB_X51_Y12; Fanout = 2; COMB Node = 'VgaSync:vgaSync\|vSync~136'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { VgaSync:vgaSync|Equal4~100 VgaSync:vgaSync|vSync~136 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.116 ns) + CELL(0.590 ns) 4.166 ns VgaSync:vgaSync\|signal~211 6 COMB LAB_X51_Y12 1 " "Info: 6: + IC(0.116 ns) + CELL(0.590 ns) = 4.166 ns; Loc. = LAB_X51_Y12; Fanout = 1; COMB Node = 'VgaSync:vgaSync\|signal~211'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.706 ns" { VgaSync:vgaSync|vSync~136 VgaSync:vgaSync|signal~211 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.679 ns) + CELL(0.738 ns) 5.583 ns VgaSync:vgaSync\|signal 7 REG LAB_X48_Y12 2 " "Info: 7: + IC(0.679 ns) + CELL(0.738 ns) = 5.583 ns; Loc. = LAB_X48_Y12; Fanout = 2; REG Node = 'VgaSync:vgaSync\|signal'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.417 ns" { VgaSync:vgaSync|signal~211 VgaSync:vgaSync|signal } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.212 ns ( 57.53 % ) " "Info: Total cell delay = 3.212 ns ( 57.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.371 ns ( 42.47 % ) " "Info: Total interconnect delay = 2.371 ns ( 42.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.583 ns" { VgaSync:vgaSync|pixel[0] VgaSync:vgaSync|Equal0~134 VgaSync:vgaSync|Equal0~135 VgaSync:vgaSync|Equal4~100 VgaSync:vgaSync|vSync~136 VgaSync:vgaSync|signal~211 VgaSync:vgaSync|signal } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X46_Y11 X57_Y21 " "Info: The peak interconnect region extends from location X46_Y11 to location X57_Y21" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/fpga/vga_可用程序/vga_colors/vga_colors.fit.smsg " "Info: Generated suppressed messages file F:/fpga/vga_可用程序/vga_colors/vga_colors.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "206 " "Info: Allocated 206 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 09 20:28:06 2009 " "Info: Processing ended: Mon Mar 09 20:28:06 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Info: Elapsed time: 00:00:27" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}