vga_colors.tan.qmsg

通过vga通讯控制显示器显示七彩条文

{ "Info" "ITDB_TH_RESULT" "clk_div2 reset_n clk -5.556 ns register " "Info: th for register \"clk_div2\" (data pin = \"reset_n\", clock pin = \"clk\") is -5.556 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.189 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.189 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J3; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.711 ns) 3.189 ns clk_div2 2 REG LC_X8_Y18_N2 31 " "Info: 2: + IC(1.009 ns) + CELL(0.711 ns) = 3.189 ns; Loc. = LC_X8_Y18_N2; Fanout = 31; REG Node = 'clk_div2'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.720 ns" { clk clk_div2 } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.36 % ) " "Info: Total cell delay = 2.180 ns ( 68.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.009 ns ( 31.64 % ) " "Info: Total interconnect delay = 1.009 ns ( 31.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { clk clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { clk clk~out0 clk_div2 } { 0.000ns 0.000ns 1.009ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.760 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset_n 1 PIN PIN_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_N5; Fanout = 1; PIN Node = 'reset_n'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset_n } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.982 ns) + CELL(0.309 ns) 8.760 ns clk_div2 2 REG LC_X8_Y18_N2 31 " "Info: 2: + IC(6.982 ns) + CELL(0.309 ns) = 8.760 ns; Loc. = LC_X8_Y18_N2; Fanout = 31; REG Node = 'clk_div2'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.291 ns" { reset_n clk_div2 } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 20.30 % ) " "Info: Total cell delay = 1.778 ns ( 20.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.982 ns ( 79.70 % ) " "Info: Total interconnect delay = 6.982 ns ( 79.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.760 ns" { reset_n clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "8.760 ns" { reset_n reset_n~out0 clk_div2 } { 0.000ns 0.000ns 6.982ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { clk clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { clk clk~out0 clk_div2 } { 0.000ns 0.000ns 1.009ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.760 ns" { reset_n clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "8.760 ns" { reset_n reset_n~out0 clk_div2 } { 0.000ns 0.000ns 6.982ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "106 " "Info: Allocated 106 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 09 20:28:45 2009 " "Info: Processing ended: Mon Mar 09 20:28:45 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}