vga_colors.tan.qmsg

通过vga通讯控制显示器显示七彩条文

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_div2 " "Info: Detected ripple clock \"clk_div2\" as buffer" {  } { { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } } { "e:/program files/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register VgaSync:vgaSync\|pixel\[1\] register VgaSync:vgaSync\|redOut 163.75 MHz 6.107 ns Internal " "Info: Clock \"clk\" has Internal fmax of 163.75 MHz between source register \"VgaSync:vgaSync\|pixel\[1\]\" and destination register \"VgaSync:vgaSync\|redOut\" (period= 6.107 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.846 ns + Longest register register " "Info: + Longest register to register delay is 5.846 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VgaSync:vgaSync\|pixel\[1\] 1 REG LC_X47_Y12_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X47_Y12_N9; Fanout = 4; REG Node = 'VgaSync:vgaSync\|pixel\[1\]'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VgaSync:vgaSync|pixel[1] } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 163 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.531 ns) + CELL(0.590 ns) 1.121 ns VgaSync:vgaSync\|Equal0~134 2 COMB LC_X47_Y12_N0 1 " "Info: 2: + IC(0.531 ns) + CELL(0.590 ns) = 1.121 ns; Loc. = LC_X47_Y12_N0; Fanout = 1; COMB Node = 'VgaSync:vgaSync\|Equal0~134'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.121 ns" { VgaSync:vgaSync|pixel[1] VgaSync:vgaSync|Equal0~134 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 165 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.114 ns) 1.668 ns VgaSync:vgaSync\|Equal0~135 3 COMB LC_X47_Y12_N6 2 " "Info: 3: + IC(0.433 ns) + CELL(0.114 ns) = 1.668 ns; Loc. = LC_X47_Y12_N6; Fanout = 2; COMB Node = 'VgaSync:vgaSync\|Equal0~135'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.547 ns" { VgaSync:vgaSync|Equal0~134 VgaSync:vgaSync|Equal0~135 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 165 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.114 ns) 2.209 ns VgaSync:vgaSync\|Equal4~100 4 COMB LC_X47_Y12_N4 8 " "Info: 4: + IC(0.427 ns) + CELL(0.114 ns) = 2.209 ns; Loc. = LC_X47_Y12_N4; Fanout = 8; COMB Node = 'VgaSync:vgaSync\|Equal4~100'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.541 ns" { VgaSync:vgaSync|Equal0~135 VgaSync:vgaSync|Equal4~100 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 187 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.853 ns) + CELL(0.114 ns) 3.176 ns VgaSync:vgaSync\|Equal4~101 5 COMB LC_X48_Y12_N0 2 " "Info: 5: + IC(0.853 ns) + CELL(0.114 ns) = 3.176 ns; Loc. = LC_X48_Y12_N0; Fanout = 2; COMB Node = 'VgaSync:vgaSync\|Equal4~101'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.967 ns" { VgaSync:vgaSync|Equal4~100 VgaSync:vgaSync|Equal4~101 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 187 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.731 ns) + CELL(0.292 ns) 4.199 ns VgaSync:vgaSync\|redOut~215 6 COMB LC_X47_Y12_N2 3 " "Info: 6: + IC(0.731 ns) + CELL(0.292 ns) = 4.199 ns; Loc. = LC_X47_Y12_N2; Fanout = 3; COMB Node = 'VgaSync:vgaSync\|redOut~215'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.023 ns" { VgaSync:vgaSync|Equal4~101 VgaSync:vgaSync|redOut~215 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.780 ns) + CELL(0.867 ns) 5.846 ns VgaSync:vgaSync\|redOut 7 REG LC_X48_Y12_N6 1 " "Info: 7: + IC(0.780 ns) + CELL(0.867 ns) = 5.846 ns; Loc. = LC_X48_Y12_N6; Fanout = 1; REG Node = 'VgaSync:vgaSync\|redOut'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.647 ns" { VgaSync:vgaSync|redOut~215 VgaSync:vgaSync|redOut } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.091 ns ( 35.77 % ) " "Info: Total cell delay = 2.091 ns ( 35.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.755 ns ( 64.23 % ) " "Info: Total interconnect delay = 3.755 ns ( 64.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.846 ns" { VgaSync:vgaSync|pixel[1] VgaSync:vgaSync|Equal0~134 VgaSync:vgaSync|Equal0~135 VgaSync:vgaSync|Equal4~100 VgaSync:vgaSync|Equal4~101 VgaSync:vgaSync|redOut~215 VgaSync:vgaSync|redOut } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "5.846 ns" { VgaSync:vgaSync|pixel[1] VgaSync:vgaSync|Equal0~134 VgaSync:vgaSync|Equal0~135 VgaSync:vgaSync|Equal4~100 VgaSync:vgaSync|Equal4~101 VgaSync:vgaSync|redOut~215 VgaSync:vgaSync|redOut } { 0.000ns 0.531ns 0.433ns 0.427ns 0.853ns 0.731ns 0.780ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.114ns 0.292ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.177 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.177 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J3; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.935 ns) 3.413 ns clk_div2 2 REG LC_X8_Y18_N2 31 " "Info: 2: + IC(1.009 ns) + CELL(0.935 ns) = 3.413 ns; Loc. = LC_X8_Y18_N2; Fanout = 31; REG Node = 'clk_div2'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.944 ns" { clk clk_div2 } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.053 ns) + CELL(0.711 ns) 8.177 ns VgaSync:vgaSync\|redOut 3 REG LC_X48_Y12_N6 1 " "Info: 3: + IC(4.053 ns) + CELL(0.711 ns) = 8.177 ns; Loc. = LC_X48_Y12_N6; Fanout = 1; REG Node = 'VgaSync:vgaSync\|redOut'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.764 ns" { clk_div2 VgaSync:vgaSync|redOut } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.09 % ) " "Info: Total cell delay = 3.115 ns ( 38.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.062 ns ( 61.91 % ) " "Info: Total interconnect delay = 5.062 ns ( 61.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.177 ns" { clk clk_div2 VgaSync:vgaSync|redOut } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "8.177 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|redOut } { 0.000ns 0.000ns 1.009ns 4.053ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.177 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.177 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J3; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.935 ns) 3.413 ns clk_div2 2 REG LC_X8_Y18_N2 31 " "Info: 2: + IC(1.009 ns) + CELL(0.935 ns) = 3.413 ns; Loc. = LC_X8_Y18_N2; Fanout = 31; REG Node = 'clk_div2'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.944 ns" { clk clk_div2 } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.053 ns) + CELL(0.711 ns) 8.177 ns VgaSync:vgaSync\|pixel\[1\] 3 REG LC_X47_Y12_N9 4 " "Info: 3: + IC(4.053 ns) + CELL(0.711 ns) = 8.177 ns; Loc. = LC_X47_Y12_N9; Fanout = 4; REG Node = 'VgaSync:vgaSync\|pixel\[1\]'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.764 ns" { clk_div2 VgaSync:vgaSync|pixel[1] } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 163 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.09 % ) " "Info: Total cell delay = 3.115 ns ( 38.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.062 ns ( 61.91 % ) " "Info: Total interconnect delay = 5.062 ns ( 61.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.177 ns" { clk clk_div2 VgaSync:vgaSync|pixel[1] } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "8.177 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|pixel[1] } { 0.000ns 0.000ns 1.009ns 4.053ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.177 ns" { clk clk_div2 VgaSync:vgaSync|redOut } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "8.177 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|redOut } { 0.000ns 0.000ns 1.009ns 4.053ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.177 ns" { clk clk_div2 VgaSync:vgaSync|pixel[1] } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "8.177 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|pixel[1] } { 0.000ns 0.000ns 1.009ns 4.053ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 163 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 116 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.846 ns" { VgaSync:vgaSync|pixel[1] VgaSync:vgaSync|Equal0~134 VgaSync:vgaSync|Equal0~135 VgaSync:vgaSync|Equal4~100 VgaSync:vgaSync|Equal4~101 VgaSync:vgaSync|redOut~215 VgaSync:vgaSync|redOut } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "5.846 ns" { VgaSync:vgaSync|pixel[1] VgaSync:vgaSync|Equal0~134 VgaSync:vgaSync|Equal0~135 VgaSync:vgaSync|Equal4~100 VgaSync:vgaSync|Equal4~101 VgaSync:vgaSync|redOut~215 VgaSync:vgaSync|redOut } { 0.000ns 0.531ns 0.433ns 0.427ns 0.853ns 0.731ns 0.780ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.114ns 0.292ns 0.867ns } "" } } { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.177 ns" { clk clk_div2 VgaSync:vgaSync|redOut } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "8.177 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|redOut } { 0.000ns 0.000ns 1.009ns 4.053ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.177 ns" { clk clk_div2 VgaSync:vgaSync|pixel[1] } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "8.177 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|pixel[1] } { 0.000ns 0.000ns 1.009ns 4.053ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "clk_div2 reset_n clk 5.608 ns register " "Info: tsu for register \"clk_div2\" (data pin = \"reset_n\", clock pin = \"clk\") is 5.608 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.760 ns + Longest pin register " "Info: + Longest pin to register delay is 8.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset_n 1 PIN PIN_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_N5; Fanout = 1; PIN Node = 'reset_n'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset_n } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.982 ns) + CELL(0.309 ns) 8.760 ns clk_div2 2 REG LC_X8_Y18_N2 31 " "Info: 2: + IC(6.982 ns) + CELL(0.309 ns) = 8.760 ns; Loc. = LC_X8_Y18_N2; Fanout = 31; REG Node = 'clk_div2'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.291 ns" { reset_n clk_div2 } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 20.30 % ) " "Info: Total cell delay = 1.778 ns ( 20.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.982 ns ( 79.70 % ) " "Info: Total interconnect delay = 6.982 ns ( 79.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.760 ns" { reset_n clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "8.760 ns" { reset_n reset_n~out0 clk_div2 } { 0.000ns 0.000ns 6.982ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.189 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.189 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J3; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.711 ns) 3.189 ns clk_div2 2 REG LC_X8_Y18_N2 31 " "Info: 2: + IC(1.009 ns) + CELL(0.711 ns) = 3.189 ns; Loc. = LC_X8_Y18_N2; Fanout = 31; REG Node = 'clk_div2'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.720 ns" { clk clk_div2 } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.36 % ) " "Info: Total cell delay = 2.180 ns ( 68.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.009 ns ( 31.64 % ) " "Info: Total interconnect delay = 1.009 ns ( 31.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { clk clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { clk clk~out0 clk_div2 } { 0.000ns 0.000ns 1.009ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.760 ns" { reset_n clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "8.760 ns" { reset_n reset_n~out0 clk_div2 } { 0.000ns 0.000ns 6.982ns } { 0.000ns 1.469ns 0.309ns } "" } } { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.189 ns" { clk clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "3.189 ns" { clk clk~out0 clk_div2 } { 0.000ns 0.000ns 1.009ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk vSync VgaSync:vgaSync\|vSync 13.636 ns register " "Info: tco from clock \"clk\" to destination pin \"vSync\" through register \"VgaSync:vgaSync\|vSync\" is 13.636 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.177 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.177 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J3; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.935 ns) 3.413 ns clk_div2 2 REG LC_X8_Y18_N2 31 " "Info: 2: + IC(1.009 ns) + CELL(0.935 ns) = 3.413 ns; Loc. = LC_X8_Y18_N2; Fanout = 31; REG Node = 'clk_div2'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.944 ns" { clk clk_div2 } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.053 ns) + CELL(0.711 ns) 8.177 ns VgaSync:vgaSync\|vSync 3 REG LC_X51_Y14_N8 2 " "Info: 3: + IC(4.053 ns) + CELL(0.711 ns) = 8.177 ns; Loc. = LC_X51_Y14_N8; Fanout = 2; REG Node = 'VgaSync:vgaSync\|vSync'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.764 ns" { clk_div2 VgaSync:vgaSync|vSync } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.09 % ) " "Info: Total cell delay = 3.115 ns ( 38.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.062 ns ( 61.91 % ) " "Info: Total interconnect delay = 5.062 ns ( 61.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.177 ns" { clk clk_div2 VgaSync:vgaSync|vSync } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "8.177 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|vSync } { 0.000ns 0.000ns 1.009ns 4.053ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 115 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.235 ns + Longest register pin " "Info: + Longest register to pin delay is 5.235 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VgaSync:vgaSync\|vSync 1 REG LC_X51_Y14_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X51_Y14_N8; Fanout = 2; REG Node = 'VgaSync:vgaSync\|vSync'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VgaSync:vgaSync|vSync } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.127 ns) + CELL(2.108 ns) 5.235 ns vSync 2 PIN PIN_V13 0 " "Info: 2: + IC(3.127 ns) + CELL(2.108 ns) = 5.235 ns; Loc. = PIN_V13; Fanout = 0; PIN Node = 'vSync'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.235 ns" { VgaSync:vgaSync|vSync vSync } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 40.27 % ) " "Info: Total cell delay = 2.108 ns ( 40.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.127 ns ( 59.73 % ) " "Info: Total interconnect delay = 3.127 ns ( 59.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.235 ns" { VgaSync:vgaSync|vSync vSync } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "5.235 ns" { VgaSync:vgaSync|vSync vSync } { 0.000ns 3.127ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.177 ns" { clk clk_div2 VgaSync:vgaSync|vSync } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "8.177 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|vSync } { 0.000ns 0.000ns 1.009ns 4.053ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.235 ns" { VgaSync:vgaSync|vSync vSync } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "5.235 ns" { VgaSync:vgaSync|vSync vSync } { 0.000ns 3.127ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}