prev_cmp_vga_colors.qmsg

通过vga通讯控制显示器显示七彩条文

{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 09 20:25:46 2009 " "Info: Processing started: Mon Mar 09 20:25:46 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vga_colors -c vga_colors --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga_colors -c vga_colors --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 56 -1 0 } } { "e:/program files/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_div2 " "Info: Detected ripple clock \"clk_div2\" as buffer" {  } { { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } } { "e:/program files/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register VgaSync:vgaSync\|pixel\[0\] register VgaSync:vgaSync\|hSync 148.08 MHz 6.753 ns Internal " "Info: Clock \"clk\" has Internal fmax of 148.08 MHz between source register \"VgaSync:vgaSync\|pixel\[0\]\" and destination register \"VgaSync:vgaSync\|hSync\" (period= 6.753 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.492 ns + Longest register register " "Info: + Longest register to register delay is 6.492 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VgaSync:vgaSync\|pixel\[0\] 1 REG LC_X47_Y22_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X47_Y22_N7; Fanout = 3; REG Node = 'VgaSync:vgaSync\|pixel\[0\]'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VgaSync:vgaSync|pixel[0] } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 163 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.533 ns) + CELL(0.590 ns) 1.123 ns VgaSync:vgaSync\|Equal0~134 2 COMB LC_X47_Y22_N6 1 " "Info: 2: + IC(0.533 ns) + CELL(0.590 ns) = 1.123 ns; Loc. = LC_X47_Y22_N6; Fanout = 1; COMB Node = 'VgaSync:vgaSync\|Equal0~134'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.123 ns" { VgaSync:vgaSync|pixel[0] VgaSync:vgaSync|Equal0~134 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 165 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.114 ns) 1.663 ns VgaSync:vgaSync\|Equal0~135 3 COMB LC_X47_Y22_N0 2 " "Info: 3: + IC(0.426 ns) + CELL(0.114 ns) = 1.663 ns; Loc. = LC_X47_Y22_N0; Fanout = 2; COMB Node = 'VgaSync:vgaSync\|Equal0~135'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.540 ns" { VgaSync:vgaSync|Equal0~134 VgaSync:vgaSync|Equal0~135 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 165 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.114 ns) 2.206 ns VgaSync:vgaSync\|Equal5~98 4 COMB LC_X47_Y22_N9 3 " "Info: 4: + IC(0.429 ns) + CELL(0.114 ns) = 2.206 ns; Loc. = LC_X47_Y22_N9; Fanout = 3; COMB Node = 'VgaSync:vgaSync\|Equal5~98'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.543 ns" { VgaSync:vgaSync|Equal0~135 VgaSync:vgaSync|Equal5~98 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 194 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.125 ns) + CELL(0.292 ns) 3.623 ns VgaSync:vgaSync\|Equal6~82 5 COMB LC_X47_Y22_N8 2 " "Info: 5: + IC(1.125 ns) + CELL(0.292 ns) = 3.623 ns; Loc. = LC_X47_Y22_N8; Fanout = 2; COMB Node = 'VgaSync:vgaSync\|Equal6~82'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.417 ns" { VgaSync:vgaSync|Equal5~98 VgaSync:vgaSync|Equal6~82 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 198 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.262 ns) + CELL(0.607 ns) 6.492 ns VgaSync:vgaSync\|hSync 6 REG LC_X46_Y22_N3 2 " "Info: 6: + IC(2.262 ns) + CELL(0.607 ns) = 6.492 ns; Loc. = LC_X46_Y22_N3; Fanout = 2; REG Node = 'VgaSync:vgaSync\|hSync'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.869 ns" { VgaSync:vgaSync|Equal6~82 VgaSync:vgaSync|hSync } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 114 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.717 ns ( 26.45 % ) " "Info: Total cell delay = 1.717 ns ( 26.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.775 ns ( 73.55 % ) " "Info: Total interconnect delay = 4.775 ns ( 73.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.492 ns" { VgaSync:vgaSync|pixel[0] VgaSync:vgaSync|Equal0~134 VgaSync:vgaSync|Equal0~135 VgaSync:vgaSync|Equal5~98 VgaSync:vgaSync|Equal6~82 VgaSync:vgaSync|hSync } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "6.492 ns" { VgaSync:vgaSync|pixel[0] VgaSync:vgaSync|Equal0~134 VgaSync:vgaSync|Equal0~135 VgaSync:vgaSync|Equal5~98 VgaSync:vgaSync|Equal6~82 VgaSync:vgaSync|hSync } { 0.000ns 0.533ns 0.426ns 0.429ns 1.125ns 2.262ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.292ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.640 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.640 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J3; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.935 ns) 3.293 ns clk_div2 2 REG LC_X8_Y16_N2 31 " "Info: 2: + IC(0.889 ns) + CELL(0.935 ns) = 3.293 ns; Loc. = LC_X8_Y16_N2; Fanout = 31; REG Node = 'clk_div2'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.824 ns" { clk clk_div2 } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.636 ns) + CELL(0.711 ns) 7.640 ns VgaSync:vgaSync\|hSync 3 REG LC_X46_Y22_N3 2 " "Info: 3: + IC(3.636 ns) + CELL(0.711 ns) = 7.640 ns; Loc. = LC_X46_Y22_N3; Fanout = 2; REG Node = 'VgaSync:vgaSync\|hSync'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.347 ns" { clk_div2 VgaSync:vgaSync|hSync } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 114 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.77 % ) " "Info: Total cell delay = 3.115 ns ( 40.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.525 ns ( 59.23 % ) " "Info: Total interconnect delay = 4.525 ns ( 59.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.640 ns" { clk clk_div2 VgaSync:vgaSync|hSync } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "7.640 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|hSync } { 0.000ns 0.000ns 0.889ns 3.636ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.640 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.640 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J3; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.935 ns) 3.293 ns clk_div2 2 REG LC_X8_Y16_N2 31 " "Info: 2: + IC(0.889 ns) + CELL(0.935 ns) = 3.293 ns; Loc. = LC_X8_Y16_N2; Fanout = 31; REG Node = 'clk_div2'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.824 ns" { clk clk_div2 } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.636 ns) + CELL(0.711 ns) 7.640 ns VgaSync:vgaSync\|pixel\[0\] 3 REG LC_X47_Y22_N7 3 " "Info: 3: + IC(3.636 ns) + CELL(0.711 ns) = 7.640 ns; Loc. = LC_X47_Y22_N7; Fanout = 3; REG Node = 'VgaSync:vgaSync\|pixel\[0\]'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.347 ns" { clk_div2 VgaSync:vgaSync|pixel[0] } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 163 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.77 % ) " "Info: Total cell delay = 3.115 ns ( 40.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.525 ns ( 59.23 % ) " "Info: Total interconnect delay = 4.525 ns ( 59.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.640 ns" { clk clk_div2 VgaSync:vgaSync|pixel[0] } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "7.640 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|pixel[0] } { 0.000ns 0.000ns 0.889ns 3.636ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.640 ns" { clk clk_div2 VgaSync:vgaSync|hSync } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "7.640 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|hSync } { 0.000ns 0.000ns 0.889ns 3.636ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.640 ns" { clk clk_div2 VgaSync:vgaSync|pixel[0] } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "7.640 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|pixel[0] } { 0.000ns 0.000ns 0.889ns 3.636ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 163 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 114 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.492 ns" { VgaSync:vgaSync|pixel[0] VgaSync:vgaSync|Equal0~134 VgaSync:vgaSync|Equal0~135 VgaSync:vgaSync|Equal5~98 VgaSync:vgaSync|Equal6~82 VgaSync:vgaSync|hSync } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "6.492 ns" { VgaSync:vgaSync|pixel[0] VgaSync:vgaSync|Equal0~134 VgaSync:vgaSync|Equal0~135 VgaSync:vgaSync|Equal5~98 VgaSync:vgaSync|Equal6~82 VgaSync:vgaSync|hSync } { 0.000ns 0.533ns 0.426ns 0.429ns 1.125ns 2.262ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.292ns 0.607ns } "" } } { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.640 ns" { clk clk_div2 VgaSync:vgaSync|hSync } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "7.640 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|hSync } { 0.000ns 0.000ns 0.889ns 3.636ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.640 ns" { clk clk_div2 VgaSync:vgaSync|pixel[0] } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "7.640 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|pixel[0] } { 0.000ns 0.000ns 0.889ns 3.636ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "clk_div2 reset_n clk 4.890 ns register " "Info: tsu for register \"clk_div2\" (data pin = \"reset_n\", clock pin = \"clk\") is 4.890 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.922 ns + Longest pin register " "Info: + Longest pin to register delay is 7.922 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset_n 1 PIN PIN_K5 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_K5; Fanout = 1; PIN Node = 'reset_n'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset_n } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.715 ns) + CELL(0.738 ns) 7.922 ns clk_div2 2 REG LC_X8_Y16_N2 31 " "Info: 2: + IC(5.715 ns) + CELL(0.738 ns) = 7.922 ns; Loc. = LC_X8_Y16_N2; Fanout = 31; REG Node = 'clk_div2'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.453 ns" { reset_n clk_div2 } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns ( 27.86 % ) " "Info: Total cell delay = 2.207 ns ( 27.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.715 ns ( 72.14 % ) " "Info: Total interconnect delay = 5.715 ns ( 72.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.922 ns" { reset_n clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "7.922 ns" { reset_n reset_n~out0 clk_div2 } { 0.000ns 0.000ns 5.715ns } { 0.000ns 1.469ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.069 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.069 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J3; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.711 ns) 3.069 ns clk_div2 2 REG LC_X8_Y16_N2 31 " "Info: 2: + IC(0.889 ns) + CELL(0.711 ns) = 3.069 ns; Loc. = LC_X8_Y16_N2; Fanout = 31; REG Node = 'clk_div2'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk clk_div2 } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 71.03 % ) " "Info: Total cell delay = 2.180 ns ( 71.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.889 ns ( 28.97 % ) " "Info: Total interconnect delay = 0.889 ns ( 28.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.069 ns" { clk clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "3.069 ns" { clk clk~out0 clk_div2 } { 0.000ns 0.000ns 0.889ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.922 ns" { reset_n clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "7.922 ns" { reset_n reset_n~out0 clk_div2 } { 0.000ns 0.000ns 5.715ns } { 0.000ns 1.469ns 0.738ns } "" } } { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.069 ns" { clk clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "3.069 ns" { clk clk~out0 clk_div2 } { 0.000ns 0.000ns 0.889ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk green VgaSync:vgaSync\|greenOut 14.243 ns register " "Info: tco from clock \"clk\" to destination pin \"green\" through register \"VgaSync:vgaSync\|greenOut\" is 14.243 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.640 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.640 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J3; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.935 ns) 3.293 ns clk_div2 2 REG LC_X8_Y16_N2 31 " "Info: 2: + IC(0.889 ns) + CELL(0.935 ns) = 3.293 ns; Loc. = LC_X8_Y16_N2; Fanout = 31; REG Node = 'clk_div2'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.824 ns" { clk clk_div2 } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.636 ns) + CELL(0.711 ns) 7.640 ns VgaSync:vgaSync\|greenOut 3 REG LC_X48_Y22_N6 1 " "Info: 3: + IC(3.636 ns) + CELL(0.711 ns) = 7.640 ns; Loc. = LC_X48_Y22_N6; Fanout = 1; REG Node = 'VgaSync:vgaSync\|greenOut'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.347 ns" { clk_div2 VgaSync:vgaSync|greenOut } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.77 % ) " "Info: Total cell delay = 3.115 ns ( 40.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.525 ns ( 59.23 % ) " "Info: Total interconnect delay = 4.525 ns ( 59.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.640 ns" { clk clk_div2 VgaSync:vgaSync|greenOut } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "7.640 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|greenOut } { 0.000ns 0.000ns 0.889ns 3.636ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 117 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.379 ns + Longest register pin " "Info: + Longest register to pin delay is 6.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VgaSync:vgaSync\|greenOut 1 REG LC_X48_Y22_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X48_Y22_N6; Fanout = 1; REG Node = 'VgaSync:vgaSync\|greenOut'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VgaSync:vgaSync|greenOut } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.271 ns) + CELL(2.108 ns) 6.379 ns green 2 PIN PIN_R11 0 " "Info: 2: + IC(4.271 ns) + CELL(2.108 ns) = 6.379 ns; Loc. = PIN_R11; Fanout = 0; PIN Node = 'green'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.379 ns" { VgaSync:vgaSync|greenOut green } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 33.05 % ) " "Info: Total cell delay = 2.108 ns ( 33.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.271 ns ( 66.95 % ) " "Info: Total interconnect delay = 4.271 ns ( 66.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.379 ns" { VgaSync:vgaSync|greenOut green } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "6.379 ns" { VgaSync:vgaSync|greenOut green } { 0.000ns 4.271ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.640 ns" { clk clk_div2 VgaSync:vgaSync|greenOut } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "7.640 ns" { clk clk~out0 clk_div2 VgaSync:vgaSync|greenOut } { 0.000ns 0.000ns 0.889ns 3.636ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.379 ns" { VgaSync:vgaSync|greenOut green } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "6.379 ns" { VgaSync:vgaSync|greenOut green } { 0.000ns 4.271ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "clk_div2 reset_n clk -4.838 ns register " "Info: th for register \"clk_div2\" (data pin = \"reset_n\", clock pin = \"clk\") is -4.838 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.069 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.069 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_J3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J3; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.711 ns) 3.069 ns clk_div2 2 REG LC_X8_Y16_N2 31 " "Info: 2: + IC(0.889 ns) + CELL(0.711 ns) = 3.069 ns; Loc. = LC_X8_Y16_N2; Fanout = 31; REG Node = 'clk_div2'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk clk_div2 } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 71.03 % ) " "Info: Total cell delay = 2.180 ns ( 71.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.889 ns ( 28.97 % ) " "Info: Total interconnect delay = 0.889 ns ( 28.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.069 ns" { clk clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "3.069 ns" { clk clk~out0 clk_div2 } { 0.000ns 0.000ns 0.889ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.922 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.922 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset_n 1 PIN PIN_K5 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_K5; Fanout = 1; PIN Node = 'reset_n'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset_n } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.715 ns) + CELL(0.738 ns) 7.922 ns clk_div2 2 REG LC_X8_Y16_N2 31 " "Info: 2: + IC(5.715 ns) + CELL(0.738 ns) = 7.922 ns; Loc. = LC_X8_Y16_N2; Fanout = 31; REG Node = 'clk_div2'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.453 ns" { reset_n clk_div2 } "NODE_NAME" } } { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns ( 27.86 % ) " "Info: Total cell delay = 2.207 ns ( 27.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.715 ns ( 72.14 % ) " "Info: Total interconnect delay = 5.715 ns ( 72.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.922 ns" { reset_n clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "7.922 ns" { reset_n reset_n~out0 clk_div2 } { 0.000ns 0.000ns 5.715ns } { 0.000ns 1.469ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.069 ns" { clk clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "3.069 ns" { clk clk~out0 clk_div2 } { 0.000ns 0.000ns 0.889ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.922 ns" { reset_n clk_div2 } "NODE_NAME" } } { "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/71/quartus/bin/Technology_Viewer.qrui" "7.922 ns" { reset_n reset_n~out0 clk_div2 } { 0.000ns 0.000ns 5.715ns } { 0.000ns 1.469ns 0.738ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "106 " "Info: Allocated 106 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 09 20:25:49 2009 " "Info: Processing ended: Mon Mar 09 20:25:49 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 5 s " "Info: Quartus II Full Compilation was successful. 0 errors, 5 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}