prev_cmp_vga_colors.qmsg

通过vga通讯控制显示器显示七彩条文

{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.30 1 0 0 " "Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 1 input, 0 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 60 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  60 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 53 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  53 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 64 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  64 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.30V 5 48 " "Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 5 total pin(s) used --  48 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.515 ns register register " "Info: Estimated most critical path is register to register delay of 5.515 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VgaSync:vgaSync\|pixel\[0\] 1 REG LAB_X47_Y22 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X47_Y22; Fanout = 3; REG Node = 'VgaSync:vgaSync\|pixel\[0\]'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { VgaSync:vgaSync|pixel[0] } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 163 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.114 ns) 0.782 ns VgaSync:vgaSync\|Equal0~134 2 COMB LAB_X47_Y22 1 " "Info: 2: + IC(0.668 ns) + CELL(0.114 ns) = 0.782 ns; Loc. = LAB_X47_Y22; Fanout = 1; COMB Node = 'VgaSync:vgaSync\|Equal0~134'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.782 ns" { VgaSync:vgaSync|pixel[0] VgaSync:vgaSync|Equal0~134 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 165 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.116 ns) + CELL(0.590 ns) 1.488 ns VgaSync:vgaSync\|Equal0~135 3 COMB LAB_X47_Y22 2 " "Info: 3: + IC(0.116 ns) + CELL(0.590 ns) = 1.488 ns; Loc. = LAB_X47_Y22; Fanout = 2; COMB Node = 'VgaSync:vgaSync\|Equal0~135'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.706 ns" { VgaSync:vgaSync|Equal0~134 VgaSync:vgaSync|Equal0~135 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 165 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.116 ns) + CELL(0.590 ns) 2.194 ns VgaSync:vgaSync\|Equal4~100 4 COMB LAB_X47_Y22 8 " "Info: 4: + IC(0.116 ns) + CELL(0.590 ns) = 2.194 ns; Loc. = LAB_X47_Y22; Fanout = 8; COMB Node = 'VgaSync:vgaSync\|Equal4~100'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.706 ns" { VgaSync:vgaSync|Equal0~135 VgaSync:vgaSync|Equal4~100 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 187 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.590 ns) 3.087 ns VgaSync:vgaSync\|Equal4~101 5 COMB LAB_X46_Y22 2 " "Info: 5: + IC(0.303 ns) + CELL(0.590 ns) = 3.087 ns; Loc. = LAB_X46_Y22; Fanout = 2; COMB Node = 'VgaSync:vgaSync\|Equal4~101'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.893 ns" { VgaSync:vgaSync|Equal4~100 VgaSync:vgaSync|Equal4~101 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 187 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.779 ns) + CELL(0.114 ns) 3.980 ns VgaSync:vgaSync\|redOut~215 6 COMB LAB_X47_Y22 3 " "Info: 6: + IC(0.779 ns) + CELL(0.114 ns) = 3.980 ns; Loc. = LAB_X47_Y22; Fanout = 3; COMB Node = 'VgaSync:vgaSync\|redOut~215'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.893 ns" { VgaSync:vgaSync|Equal4~101 VgaSync:vgaSync|redOut~215 } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.867 ns) 5.515 ns VgaSync:vgaSync\|redOut 7 REG LAB_X46_Y22 1 " "Info: 7: + IC(0.668 ns) + CELL(0.867 ns) = 5.515 ns; Loc. = LAB_X46_Y22; Fanout = 1; REG Node = 'VgaSync:vgaSync\|redOut'" {  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.535 ns" { VgaSync:vgaSync|redOut~215 VgaSync:vgaSync|redOut } "NODE_NAME" } } { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.865 ns ( 51.95 % ) " "Info: Total cell delay = 2.865 ns ( 51.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.650 ns ( 48.05 % ) " "Info: Total interconnect delay = 2.650 ns ( 48.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.515 ns" { VgaSync:vgaSync|pixel[0] VgaSync:vgaSync|Equal0~134 VgaSync:vgaSync|Equal0~135 VgaSync:vgaSync|Equal4~100 VgaSync:vgaSync|Equal4~101 VgaSync:vgaSync|redOut~215 VgaSync:vgaSync|redOut } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X35_Y22 X45_Y33 " "Info: The peak interconnect region extends from location X35_Y22 to location X45_Y33" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}