prev_cmp_vga_colors.qmsg

通过vga通讯控制显示器显示七彩条文

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 09 20:24:44 2009 " "Info: Processing started: Mon Mar 09 20:24:44 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vga_colors -c vga_colors " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_colors -c vga_colors" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_CREATED_IMPLICIT_NET" "lineWire vga_colors.v(82) " "Warning (10236): Verilog HDL Implicit Net warning at vga_colors.v(82): created implicit net for \"lineWire\"" {  } { { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 82 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_colors.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file vga_colors.v" { { "Info" "ISGN_ENTITY_NAME" "1 VgaColors " "Info: Found entity 1: VgaColors" {  } { { "vga_colors.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 49 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_sync.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file vga_sync.v" { { "Info" "ISGN_ENTITY_NAME" "1 VgaSync " "Info: Found entity 1: VgaSync" {  } { { "vga_sync.v" "" { Text "F:/fpga/vga_可用程序/vga_colors/vga_sync.v" 100 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "VgaColors " "Info: Elaborating entity \"VgaColors\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VgaSync VgaSync:vgaSync " "Info: Elaborating entity \"VgaSync\" for hierarchy \"VgaSync:vgaSync\"" {  } { { "vga_colors.v" "vgaSync" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 87 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "line vgaSync 1 12 " "Warning: Port \"line\" on the entity instantiation of \"vgaSync\" is connected to a signal of width 1. The formal width of the signal in the module is 12.  Extra bits will be left dangling without any fanout logic." {  } { { "vga_colors.v" "vgaSync" { Text "F:/fpga/vga_可用程序/vga_colors/vga_colors.v" 87 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "81 " "Info: Implemented 81 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "74 " "Info: Implemented 74 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "135 " "Info: Allocated 135 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 09 20:24:49 2009 " "Info: Processing ended: Mon Mar 09 20:24:49 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 09 20:24:51 2009 " "Info: Processing started: Mon Mar 09 20:24:51 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off vga_colors -c vga_colors " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vga_colors -c vga_colors" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "vga_colors EP1C20F324C8 " "Info: Selected device EP1C20F324C8 for design \"vga_colors\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}