vga_colors.tan.rpt

通过vga通讯控制显示器显示七彩条文

; N/A                                     ; 233.05 MHz ( period = 4.291 ns )                    ; VgaSync:vgaSync|pixel[3]  ; VgaSync:vgaSync|line[11]  ; clk        ; clk      ; None                        ; None                      ; 4.030 ns                ;
; N/A                                     ; 233.05 MHz ( period = 4.291 ns )                    ; VgaSync:vgaSync|pixel[3]  ; VgaSync:vgaSync|line[10]  ; clk        ; clk      ; None                        ; None                      ; 4.030 ns                ;
; N/A                                     ; 233.05 MHz ( period = 4.291 ns )                    ; VgaSync:vgaSync|pixel[3]  ; VgaSync:vgaSync|line[6]   ; clk        ; clk      ; None                        ; None                      ; 4.030 ns                ;
; N/A                                     ; 233.32 MHz ( period = 4.286 ns )                    ; VgaSync:vgaSync|pixel[0]  ; VgaSync:vgaSync|pixel[10] ; clk        ; clk      ; None                        ; None                      ; 4.025 ns                ;
; N/A                                     ; 233.48 MHz ( period = 4.283 ns )                    ; VgaSync:vgaSync|pixel[0]  ; VgaSync:vgaSync|pixel[7]  ; clk        ; clk      ; None                        ; None                      ; 4.022 ns                ;
; N/A                                     ; 233.81 MHz ( period = 4.277 ns )                    ; VgaSync:vgaSync|pixel[0]  ; VgaSync:vgaSync|pixel[6]  ; clk        ; clk      ; None                        ; None                      ; 4.016 ns                ;
; N/A                                     ; 234.25 MHz ( period = 4.269 ns )                    ; VgaSync:vgaSync|line[8]   ; VgaSync:vgaSync|line[9]   ; clk        ; clk      ; None                        ; None                      ; 4.008 ns                ;
; N/A                                     ; 234.36 MHz ( period = 4.267 ns )                    ; VgaSync:vgaSync|line[1]   ; VgaSync:vgaSync|line[2]   ; clk        ; clk      ; None                        ; None                      ; 4.006 ns                ;
; N/A                                     ; 234.52 MHz ( period = 4.264 ns )                    ; VgaSync:vgaSync|pixel[5]  ; VgaSync:vgaSync|signal    ; clk        ; clk      ; None                        ; None                      ; 4.003 ns                ;
; N/A                                     ; 234.63 MHz ( period = 4.262 ns )                    ; VgaSync:vgaSync|pixel[9]  ; VgaSync:vgaSync|hSync     ; clk        ; clk      ; None                        ; None                      ; 4.001 ns                ;
; N/A                                     ; 234.85 MHz ( period = 4.258 ns )                    ; VgaSync:vgaSync|line[0]   ; VgaSync:vgaSync|line[2]   ; clk        ; clk      ; None                        ; None                      ; 3.997 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                           ;                           ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------+
; tsu                                                               ;
+-------+--------------+------------+---------+----------+----------+
; Slack ; Required tsu ; Actual tsu ; From    ; To       ; To Clock ;
+-------+--------------+------------+---------+----------+----------+
; N/A   ; None         ; 5.608 ns   ; reset_n ; clk_div2 ; clk      ;
+-------+--------------+------------+---------+----------+----------+


+-----------------------------------------------------------------------------------+
; tco                                                                               ;
+-------+--------------+------------+--------------------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From                     ; To    ; From Clock ;
+-------+--------------+------------+--------------------------+-------+------------+
; N/A   ; None         ; 13.636 ns  ; VgaSync:vgaSync|vSync    ; vSync ; clk        ;
; N/A   ; None         ; 13.497 ns  ; VgaSync:vgaSync|greenOut ; green ; clk        ;
; N/A   ; None         ; 13.468 ns  ; VgaSync:vgaSync|redOut   ; red   ; clk        ;
; N/A   ; None         ; 13.225 ns  ; VgaSync:vgaSync|blueOut  ; blue  ; clk        ;
; N/A   ; None         ; 12.818 ns  ; VgaSync:vgaSync|hSync    ; hSync ; clk        ;
+-------+--------------+------------+--------------------------+-------+------------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+---------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To       ; To Clock ;
+---------------+-------------+-----------+---------+----------+----------+
; N/A           ; None        ; -5.556 ns ; reset_n ; clk_div2 ; clk      ;
+---------------+-------------+-----------+---------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Mon Mar 09 20:28:43 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga_colors -c vga_colors --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk_div2" as buffer
Info: Clock "clk" has Internal fmax of 163.75 MHz between source register "VgaSync:vgaSync|pixel[1]" and destination register "VgaSync:vgaSync|redOut" (period= 6.107 ns)
    Info: + Longest register to register delay is 5.846 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X47_Y12_N9; Fanout = 4; REG Node = 'VgaSync:vgaSync|pixel[1]'
        Info: 2: + IC(0.531 ns) + CELL(0.590 ns) = 1.121 ns; Loc. = LC_X47_Y12_N0; Fanout = 1; COMB Node = 'VgaSync:vgaSync|Equal0~134'
        Info: 3: + IC(0.433 ns) + CELL(0.114 ns) = 1.668 ns; Loc. = LC_X47_Y12_N6; Fanout = 2; COMB Node = 'VgaSync:vgaSync|Equal0~135'
        Info: 4: + IC(0.427 ns) + CELL(0.114 ns) = 2.209 ns; Loc. = LC_X47_Y12_N4; Fanout = 8; COMB Node = 'VgaSync:vgaSync|Equal4~100'
        Info: 5: + IC(0.853 ns) + CELL(0.114 ns) = 3.176 ns; Loc. = LC_X48_Y12_N0; Fanout = 2; COMB Node = 'VgaSync:vgaSync|Equal4~101'
        Info: 6: + IC(0.731 ns) + CELL(0.292 ns) = 4.199 ns; Loc. = LC_X47_Y12_N2; Fanout = 3; COMB Node = 'VgaSync:vgaSync|redOut~215'
        Info: 7: + IC(0.780 ns) + CELL(0.867 ns) = 5.846 ns; Loc. = LC_X48_Y12_N6; Fanout = 1; REG Node = 'VgaSync:vgaSync|redOut'
        Info: Total cell delay = 2.091 ns ( 35.77 % )
        Info: Total interconnect delay = 3.755 ns ( 64.23 % )