ti_phy_top.if.vrh

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// ===========================================================================
// File    : ti_phy_top.if.vrh
// Author  : cwinward
// Date    : Mon Dec 3 11:03:46 MST 2007
// Project : TI PHY design
//
// Copyright (c) notice
// This code adheres to the GNU public license
//
// ===========================================================================
//
// $Id: ti_phy_top.if.vrh,v 1.2 2008-01-15 03:25:07 cmagleby Exp $
//
// ===========================================================================
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2007/12/05 18:37:07  cmagleby
// importing tb files
//
//
// ===========================================================================
// Function : .This is the interface file linking verilog with VERA
//
// ===========================================================================
// ===========================================================================
#ifndef INC_TI_PHY_TOP_IF_VRH
#define INC_TI_PHY_TOP_IF_VRH

  interface ti_phy_top {
    input               rxclk CLOCK;
    //input   [9:0]       t1_count        PSAMPLE #-1 verilog_node "dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count"; 
    output  		clk_50mhz	OUTPUT_EDGE OUTPUT_SKEW;
    output  [1:0]	PUSH_BUTTON	OUTPUT_EDGE OUTPUT_SKEW;
    output  		FPGA_RESET_n	OUTPUT_EDGE OUTPUT_SKEW;
    output  		PERST_n         OUTPUT_EDGE OUTPUT_SKEW;
    output  [15:0]	rxdata16	OUTPUT_EDGE OUTPUT_SKEW;
    output  [1:0]	rxdatak16	OUTPUT_EDGE OUTPUT_SKEW;
    output  		rxvalid16	OUTPUT_EDGE OUTPUT_SKEW;
    output  		rxidle16	OUTPUT_EDGE OUTPUT_SKEW;
    output  [2:0]	rxstatus	OUTPUT_EDGE OUTPUT_SKEW;
    output  		phystatus	OUTPUT_EDGE OUTPUT_SKEW;
    input [7:0]	        LED	INPUT_EDGE  INPUT_SKEW;
    input 		txclk	INPUT_EDGE  INPUT_SKEW;
    input [15:0]	txdata16	INPUT_EDGE  INPUT_SKEW;
    input [1:0]	        txdatak16	INPUT_EDGE  INPUT_SKEW;
    input 		txidle16	INPUT_EDGE  INPUT_SKEW;
    input 		rxdet_loopb	INPUT_EDGE  INPUT_SKEW;
    input 		txcomp	INPUT_EDGE  INPUT_SKEW;
    input 		rxpol	INPUT_EDGE  INPUT_SKEW;
    input 		phy_reset_n	INPUT_EDGE  INPUT_SKEW;
    input [1:0]	pwrdwn	INPUT_EDGE  INPUT_SKEW;
    input [16:0]	sram_addr	INPUT_EDGE  INPUT_SKEW;
    input 		sram_adscn	INPUT_EDGE  INPUT_SKEW;
    input 		sram_adspn	INPUT_EDGE  INPUT_SKEW;
    input 		sram_advn	INPUT_EDGE  INPUT_SKEW;
    input [3:0]	sram_ben	INPUT_EDGE  INPUT_SKEW;
    input [2:0]	sram_ce	INPUT_EDGE  INPUT_SKEW;
    input 		sram_clk	INPUT_EDGE  INPUT_SKEW;
    input 		sram_gwn	INPUT_EDGE  INPUT_SKEW;
    input 		sram_mode	INPUT_EDGE  INPUT_SKEW;
    input 		sram_oen	INPUT_EDGE  INPUT_SKEW;
    input 		sram_wen	INPUT_EDGE  INPUT_SKEW;
    input 		sram_zz	INPUT_EDGE  INPUT_SKEW;
    inout  [35:0]	sram_data	INPUT_EDGE  INPUT_SKEW OUTPUT_EDGE OUTPUT_SKEW;
  } // end of interface ti_phy_top

#endif