reg.vhd

来自「vhdl code for GIF Image Viewer」· VHDL 代码 · 共 36 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity reg is
	 Generic ( size : integer := 8 );
	 Port ( d : in std_logic_vector(size-1 downto 0);
           q : out std_logic_vector(size-1 downto 0);
           rstL : in std_logic;
           clk : in std_logic;
           ce : in std_logic);
end reg;

architecture Behavioral of reg is

begin

process (clk, rstL)
	variable data : std_logic_vector(size-1 downto 0);
begin
	if (rstL = '0') then
		data := (others => '0');
	elsif (clk'event and clk = '1') then
		if (ce = '1') then 
			data := d;
        elsif (ce = '0') then data:= data;
		end if;
	end if;

	q <= data;
end process;


end Behavioral;