vgatest.vhd

vhdl code for GIF Image Viewer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity vgatest is
	port
	(
		clock : in std_logic;
		resetN : in std_logic;
		rdn, wrn : out std_logic;
		rs : inout std_logic_vector(2 downto 0);
		ramdac_data : inout std_logic_vector(7 downto 0);
		hsyncb : buffer std_logic;
		vsyncb : buffer std_logic;
		raddr : out std_logic_vector(18 downto 0);
		rdata : inout std_logic_vector(15 downto 0);
		rcen, rwen, roen : out std_logic;
		pixelclk : out std_logic;
		pblank : out std_logic;
		status : out std_logic_vector(1 downto 0);
		pixel : out std_logic_vector(7 downto 0);
		triste : out std_logic
	);
end vgatest;

architecture Behavioral of vgatest is
component vgamem is
	port
	(
		reset: in std_logic;	-- reset
		clock: in std_logic;	-- VGA dot clock
		hsyncb: buffer std_logic;	-- horizontal (line) sync
		vsyncb: buffer std_logic;	-- vertical (frame) sync
		addr: out std_logic_vector(19 downto 0);	-- address into video RAM
		oeb: out std_logic;		-- video RAM output enable
		web: out std_logic;		-- video RAM write enable
		pixelclk : out std_logic;
		pblank : out std_logic;

		imwidth, imheight : in std_logic_vector(9 downto 0)	
	);
end component;

	COMPONENT memreadmux
	PORT(
		paletteAddr : IN std_logic_vector(19 downto 0);
		paletteWriteData : IN std_logic_vector(15 downto 0);
		paletteOEN : IN std_logic;
		paletteWEN : IN std_logic;
		lzwAddr : IN std_logic_vector(19 downto 0);
		lzwWriteData : IN std_logic_vector(15 downto 0);
		lzwOEN : IN std_logic;
		lzwWEN : IN std_logic;
		headersAddr : IN std_logic_vector(19 downto 0);
		headersWriteData : IN std_logic_vector(15 downto 0);
		headersOEN : IN std_logic;
		headersWEN : IN std_logic;
		vgaAddr : IN std_logic_vector(19 downto 0);
		vgaWriteData : IN std_logic_vector(15 downto 0);
		vgaOEN : IN std_logic;
		vgaWEN : IN std_logic;
		sel : IN std_logic_vector(1 downto 0);    
		lData : INOUT std_logic_vector(15 downto 0);
		rData : INOUT std_logic_vector(15 downto 0);      
		lAddr : OUT std_logic_vector(18 downto 0);
		lOEN : OUT std_logic;
		lWEN : OUT std_logic;
		lCEN : OUT std_logic;
		rAddr : OUT std_logic_vector(18 downto 0);
		rOEN : OUT std_logic;
		rWEN : OUT std_logic;
		rCEN : OUT std_logic;
		paletteReadData : OUT std_logic_vector(15 downto 0);
		lzwReadData : OUT std_logic_vector(15 downto 0);
		headersReadData : OUT std_logic_vector(15 downto 0);
		vgaReadData : OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;

COMPONENT prgramdacver2
PORT(
	clk : IN std_logic;
	rstn : IN std_logic;
	start : IN std_logic;
	readData : IN std_logic_vector(15 downto 0);
	startAddr : IN std_logic_vector(20 downto 0);
	tableSize : IN std_logic_vector(2 downto 0);    
	RS : INOUT std_logic_vector(2 downto 0);
	data : INOUT std_logic_vector(7 downto 0);      
	done : OUT std_logic;
	WRn : OUT std_logic;
	RDn : OUT std_logic;
	oen : OUT std_logic;
	wen : OUT std_logic;
	readAddr : OUT std_logic_vector(19 downto 0)
	);
END COMPONENT;

signal clk, reset, oeb, web, paletteOEn, paletteWEn, palette_start, palette_done : std_logic;
signal addr, paletteAddr  : std_logic_vector(19 downto 0);
signal paletteReadData : std_logic_vector(15 downto 0);
signal memSel : std_logic_vector(1 downto 0);

begin

reset <= not resetN;

--raddr <= (others => '0');
pixel <= "10101010";
rcen <= '1';
triste <= '1';

myvga : vgamem
PORT MAP(
	reset => reset,
	clock => clk,
	hsyncb => hsyncb,
	vsyncb => vsyncb,
	addr => addr,
	oeb => oeb,
	web => web,
	pixelclk => pixelclk,
	imwidth => "1001011000",
	imheight => "0110010000",
	pblank => pblank
	);

Inst_memreadmux: memreadmux PORT MAP(
		lAddr => open,
		lData => open,
		lOEN => open,
		lWEN => open,
		lCEN => open,
		rAddr => open, --raddr,
		rData => open, --rdata,
		rOEN => open, --roen,
		rWEN => open, --rwen,
		rCEN => open, --rcen,
		paletteAddr => paletteAddr,
		paletteReadData => paletteReadData,
		paletteWriteData => "ZZZZZZZZZZZZZZZZ",
		paletteOEN => paletteOEn,
		paletteWEN => paletteWEn,
		lzwAddr => "00000000000000000000",
		lzwReadData => open,
		lzwWriteData => "ZZZZZZZZZZZZZZZZ",
		lzwOEN => '1',
		lzwWEN => '1',
		headersAddr => "00000000000000000000",
		headersReadData => open,
		headersWriteData => "ZZZZZZZZZZZZZZZZ",
		headersOEN => '1',
		headersWEN => '1',
		vgaAddr => addr,
		vgaReadData => open,
		vgaWriteData => "ZZZZZZZZZZZZZZZZ",
		vgaOEN => oeb,
		vgaWEN => web,
		sel => memSel
	);

	Inst_prgramdacver2: prgramdacver2 PORT MAP(
		clk => clk,
		rstn => resetN,
		start => palette_start,
		done => palette_done,
		WRn => wrn,
		RDn => rdn,
		RS => rs,
		data => ramdac_data,
		oen => paletteoen,
		wen => palettewen,
		readAddr => paletteAddr,
		readData => paletteReadData,
		startAddr => "111111110000000000000",
		tableSize => "111" 
	);

	process (clk, reset)
		variable state : integer;
	begin
		if (clk'event and clk = '1') then
			if (reset = '1') then
				palette_start <= '0';
				memSel <= "00";
				state := 0;
				status <= "00";
			elsif (state = 0) then
				memSel <= "00";
				palette_start <= '1';
				state := 1;
				status <= "00";
			elsif (state = 1) then
				palette_start <= '0';
				state := 2;
				status <= "01";
			elsif (state = 2) then
				if (palette_done = '1') then
					state := 3;
				end if;
				status <= "10";
			elsif (state = 3) then
				memSel <= "11";
				status <= "11";
			end if;
		end if;
	end process;

	process (clock)
		variable x : std_logic := '0';
	begin
		if (clock'event and clock = '1') then
			x := not x;
			if (x = '1') then
				clk <= '1';
			else
				clk <= '0';
			end if;
		end if;
	end process;


end Behavioral;