adder.vhd

来自「vhdl code for GIF Image Viewer」· VHDL 代码 · 共 20 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adder is
	Generic ( size : integer := 8);
	Port ( a : in std_logic_vector(size-1 downto 0);
           b : in std_logic_vector(size-1 downto 0);
           s : out std_logic_vector(size-1 downto 0));
end adder;

architecture Behavioral of adder is

begin

s <= a + b;

end Behavioral;