📄 mux2.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux2 is
Generic ( size : integer := 8 );
Port ( d0 : in std_logic_vector(size-1 downto 0);
d1 : in std_logic_vector(size-1 downto 0);
s : in std_logic;
o : out std_logic_vector(size-1 downto 0));
end mux2;
architecture Behavioral of mux2 is
signal ss : std_logic_vector(size-1 downto 0);
begin
ss <= (others => s);
o <= (d1 and ss) or (d0 and not ss);
end Behavioral;
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