📄 counter.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
generic ( size : integer := 16);
Port (cop: IN std_logic_vector(1 downto 0);
reset: IN std_logic;
clk: IN std_logic;
outdata: OUT std_logic_vector(size-1 downto 0)
);
end counter;
architecture Behavioral of counter is
begin
PROCESS (clk)
variable output: integer;
begin
if (clk'EVENT and clk='1') THEN
if (reset = '1') THEN output := 0; END IF;
if (cop = "00") THEN output := output; END IF;
if (cop = "01") THEN output := output + 1; END IF;
end if;
outdata <= conv_std_logic_vector(output, size);
end process;
end Behavioral;
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