📄 mux6.vhi
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-- VHDL Instantiation Created from source file mux6.vhd -- 19:39:22 03/22/2004
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
COMPONENT mux6
PORT(
d0 : IN std_logic_vector(7 downto 0);
d1 : IN std_logic_vector(7 downto 0);
d2 : IN std_logic_vector(7 downto 0);
d3 : IN std_logic_vector(7 downto 0);
d4 : IN std_logic_vector(7 downto 0);
d5 : IN std_logic_vector(7 downto 0);
s : IN std_logic_vector(2 downto 0);
o : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
Inst_mux6: mux6 PORT MAP(
d0 => ,
d1 => ,
d2 => ,
d3 => ,
d4 => ,
d5 => ,
s => ,
o =>
);
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