hicolvga.vhd

VHDL Checkers Implementation by Ibrahim Elbouchikhi Amir Nader-Tehrani

-------------------------------------------------------------------------------
-- hicolvga.vhd
--
-- Author(s):     Ibrahim Elbouchiki and Amir Nader-Tehrani
-- Created:       March 2004
-- 
-- This code acts as a top level for the Checkers and VGA output project.  
-- The process of Checkers Game and all its set of controls are set in this file.
-- The RAMDAC should be set up to program high colour dual-edged mode.  
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.all;

entity vga is
    port (
        clk: in STD_LOGIC;								-- clock
        rstn: in STD_LOGIC;								-- asynchronous active low reset
        pixel: out STD_LOGIC_VECTOR (7 downto 0);		-- RAMDAC pixel lines
        blankn: out STD_LOGIC;							-- RAMDAC blank signal
        RDn: out STD_LOGIC;								-- RAMDAC RDn connection
		  WRn: out STD_LOGIC;        						-- RAMDAC WRn connection
		  RAMDACD: inout STD_LOGIC_VECTOR (7 downto 0);	-- RAMDAC data lines
		  RS: inout STD_LOGIC_VECTOR (2 downto 0);		-- RAMDAC RS lines
        hsync: out STD_LOGIC;							-- horizontal sync for monitor
        vsync: out STD_LOGIC;							-- vertical sync for monitor
        triste: out STD_LOGIC;							-- signal to tristate ethernet PHY
        rramce: out STD_LOGIC;							-- right ram chip enable
        pixelclk: out STD_LOGIC;							-- RAMDAC pixel clock
		  NW: in STD_LOGIC;									--The direction recieved from board. Indicates North West
		  NE: in STD_LOGIC;									--The direction recieved from board. Indicates North East
		  SE: in STD_LOGIC;									--The direction recieved from board. Indicates South East
		  SW: in STD_LOGIC;									--The direction recieved from board. Indicates South West							
		  X: in STD_LOGIC_VECTOR(1 downto 0);			--Indicates position of the pin to be moved on the Rows
		  Y: in STD_LOGIC_VECTOR(1 downto 0);			--Indicates position of the pin to be moved on the coloumns
		  whereto: out STD_LOGIC_VECTOR(3 downto 0); --Indicates where the move direction is and shows it to board
		  playerout: out STD_LOGIC;
		  --playout: out std_logic;
		  player: in std_logic;								--Indicates the turn of the playr to play
		  moveout: out std_logic
    );
end vga;

architecture vga_arch of vga is

-- control VGA signals
component vgacore 
	generic (
		H_SIZE : integer;							-- horizontal size of input image, MAX 800
		V_SIZE : integer							-- vertical size of input image, MAX 600
	);
	port
	(
		reset: in std_logic;						-- asynchronous active low reset
		clock: in std_logic;						-- clock
		hsyncb: buffer std_logic;					-- horizontal (line) sync
		vsyncb: out std_logic;						-- vertical (frame) sync
		latch: out STD_LOGIC;						-- latches new rgb value
		enable: out STD_LOGIC;						-- enable/ground RGB output lines
		hloc: out std_logic_vector(9 downto 0);		-- horizontal address to be decoded for video RAM
		vloc: out std_logic_vector(9 downto 0)		-- vertical address to be decoded for video RAM
	);
end component;

-- Program the RAMDAC
component prgramdacver2
    port (
        clk: in STD_LOGIC;							-- Clock
        rstn: in STD_LOGIC;							-- Asynchronous active low reset
        start: in STD_LOGIC;						-- Start signal
        done: out STD_LOGIC;						-- Asserted when programming is finished
        WRn: out STD_LOGIC;							-- Write line to RAMDAC (active low)
        RDn: out STD_LOGIC;							-- Read line to RAMDAC (active low)
        RS: inout STD_LOGIC_VECTOR (2 downto 0);	-- Register select lines to the RAMDAC
        data: inout STD_LOGIC_VECTOR (7 downto 0)	-- Bidirectional data line to RAMDAC
    );
end component;


constant pinnums:std_logic_vector(2 downto 0):="010"; --The constant number of pins in the game for each player

-- State signals
type STATETYPE is (stReset, stWaste1, stWaste2, stWaste3, stWait, stForever);
signal presState: STATETYPE;

-- This is the place where the One Dimm. Array is defined used to represent the board
type boardType is array ( 0 to 15 ) of std_logic_vector( 1 downto 0);
signal Board: boardType;

--Set of states for the control of the game and moves on the board
type GAMESTATETYPE is (player1,player2,win1,win2,init,stDelay1,stDelay2);
signal presGameState: GAMESTATETYPE;

-- signals so that hsync and vsync can be read
signal hsyncInt : STD_LOGIC;
signal vsyncInt : STD_LOGIC;

-- signals to cue different processes
signal startProg : STD_LOGIC;
signal startVGA : STD_LOGIC;
signal resetVGA : STD_LOGIC;
signal done : STD_LOGIC;

-- signals to generate test pattern
signal hloc : std_logic_vector(9 downto 0);				-- horizontal location of each pixel
signal vloc : std_logic_vector(9 downto 0);				-- vertical location of each pixel
signal pixelData : STD_LOGIC_VECTOR(15 downto 0);		-- colour to write for each pixel
signal currentcolor: std_logic_vector(1 downto 0); -- current background color
signal temppin: std_logic_vector(1 downto 0);	--detemines the previous state of the cell
signal resetGame , won1 , won2 , show1 , show2: std_logic;	--Set of the signals raised to control the state transition
signal counter1 , counter2 : std_logic_vector(2 downto 0):="001";	-- The holders for the number of eaten pins by each player 
signal canMove: std_logic:= '0' ;						-- Indicates weather a move should be allowed or not
signal count: std_logic_vector(3 downto 0);			--The counter kept to avoid reentering the move IF statement


begin
	-- VGA controller
	cycler : vgacore 
	generic map (
		H_SIZE => 256,
		V_SIZE => 256
	)
	port map(
		reset => resetVGA,
		clock => clk,
		hsyncb => hsyncInt,
		vsyncb => vsyncInt,
		latch => open,
		enable => blankn,
		hloc => hloc,
		vloc => vloc
	);
    
    -- RAMDAC programmer
    RAMDACprog : prgramdacver2 port map (
        clk => clk,
        rstn => rstn,
        start => startProg,
        done => done,
        WRn => WRn,
        RDn => RDn,
        RS => RS,
        data => RAMDACD
    );
	
	-- This is a simple mealy state machine that cues the VGA controller
	-- when the RAMDAC is finished programming
	process(clk, rstn)
	begin
		if rstn = '0' then
			presState <= stReset;
		elsif clk'event AND clk = '1' then
			case presState is
				when stReset =>
					presState <= stWaste1;
				when stWaste1 =>
					presState <= stWaste2;
				when stWaste2 =>
					presState <= stWaste3;
				when stWaste3 =>
					presState <= stWait;
				when stWait =>
					if done = '0' then
						presState <= stWait;
					else
						presState <= stForever;
					end if;
				when stForever =>
					presState <= stForever;
			end case;
		end if;
	end process;
	
	process(presState)
	begin
		case presState is
			when stReset =>
				startProg <= '1';
				startVGA <= '0';
			when stWaste1 =>
				startProg <= '1';
				startVGA <= '0';
			when stWaste2 =>
				startProg <= '1';
				startVGA <= '0';
			when stWaste3 =>
				startProg <= '1';
				startVGA <= '0';
			when stWait =>
				startProg <= '0';
				startVGA <= '0';
			when stForever =>
				startProg <= '0';
				startVGA <= '1';
		end case;
	end process;


--This is the State machine used in order to implement the control subsystem of the design
pixelData(15) <= '0';

process(clk,rstn)

variable move : std_logic_vector(3 downto 0);

begin 

	move := SE & SW & NW & NE;
		if rstn = '0' then							--If rstn is raised by the user ,go to the init state
			presGameState <= init;
		elsif clk'event and clk='1' then    	--on the rising edge of the clock
			case presGameState is
				when init => 							--in the init state initialize the board and reset the count
					presGameState <= player1;		
					resetGame <= '1';
					count <="0000";
				when player1 =>							--Move to player state is done unconditionally after init state
					if ( won1 = '1' ) then				-- if the game is won by player 1 move to win state for this player
						presGameState <= win1;
					elsif not (move = "1111") then 
						presGameState <= stDelay1;		--If the game has not been won yet but a move is made move to delay state for player 1
					else 
						presGameState <= player1;		--otherwise stay in the player1 state until a move is made
					end if;
					canMove <= '1';						
					won1 <= '0';
				when stDelay1 =>							
					if move ="1111" then					-- if the push bottom is released, move to player 2 state
						presGameState <= player2;
					else
						presGameState <= stDelay1;		-- if the push bottom is not released yet stay until it is released
					end if;
					count <= "0000";
					canMove<='0';
				when player2 =>
					if ( won2 = '1' ) then				-- if the game is won by player 1 move to win state for this player
						presGameState <= win2;
					elsif not (move = "1111") then 
						presGameState <= stDelay2;		--If the game has not been won yet but a move is made move to delay state for player 1
					else 
						presGameState <= player2;		--otherwise stay in the player1 state until a move is made
					end if;
					canMove <= '1';
					won2 <= '0';
				when stDelay2 =>
					if move ="1111" then					-- if the push bottom is released, move to player 1 state
						presGameState <= player1;
					else
						presGameState <= stDelay2;		-- if the push bottom is not released yet stay until it is released
					end if;
					count <= "0000";
					canMove<='0';
				when win1 =>								--A move to this state is made if player one wins the game