hssdrc_decoder.v

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv

  output chid_t        dec1_chid          ;     
  output sdram_burst_t dec1_burst         ; 
  //
  output logic         dec2_pre_all       ;   
  output logic         dec2_refr          ;   
  output logic         dec2_pre           ;   
  output logic         dec2_act           ;   
  output logic         dec2_read          ;   
  output logic         dec2_write         ;   
  input  wire          dec2_pre_all_enable;
  input  wire          dec2_refr_enable   ;
  input  wire          dec2_pre_enable    ;
  input  wire          dec2_act_enable    ;
  input  wire          dec2_read_enable   ;
  input  wire          dec2_write_enable  ;
  output logic         dec2_locked        ;     
  output logic         dec2_last          ;     
  output rowa_t        dec2_rowa          ;     
  output cola_t        dec2_cola          ;     
  output ba_t          dec2_ba            ;     
  output chid_t        dec2_chid          ;     
  output sdram_burst_t dec2_burst         ; 
   
  //-------------------------------------------------------------------------------------------------- 
  //
  //-------------------------------------------------------------------------------------------------- 

  ba_t    ba_latched  ;
  rowa_t  rowa_latched;

  //
  // local state ba_map signals 
  // 

  wire state0__ba_map_update      ;
  wire state0__ba_map_clear       ;
  wire state0__ba_map_pre_act_rw  ;
  wire state0__ba_map_act_rw      ;
  wire state0__ba_map_rw          ;
  wire state0__ba_map_all_close   ;

  wire state1__ba_map_update      ;
  wire state1__ba_map_clear       ;
  wire state1__ba_map_pre_act_rw  ;
  wire state1__ba_map_act_rw      ;
  wire state1__ba_map_rw          ;
  wire state1__ba_map_all_close   ;

  wire state2__ba_map_update      ;
  wire state2__ba_map_clear       ;
  wire state2__ba_map_pre_act_rw  ;
  wire state2__ba_map_act_rw      ;
  wire state2__ba_map_rw          ;
  wire state2__ba_map_all_close   ;

  //-------------------------------------------------------------------------------------------------- 
  // we can capture bank map data into register, becouse we have +1 tick in FSM 
  // for bank map decoding we can take data from any arbiter channel 
  //-------------------------------------------------------------------------------------------------- 

  always_ff @(posedge clk) begin : ba_map_data_register 
    ba_latched    <= arb0_ba; 
    rowa_latched  <= arb0_rowa; 
  end 

  //
  //
  //

  assign ba_map_ba     = ba_latched; 
  assign ba_map_rowa   = rowa_latched;
  assign ba_map_update = state0__ba_map_update | state1__ba_map_update | state2__ba_map_update ; 
  assign ba_map_clear  = state0__ba_map_clear  | state1__ba_map_clear  | state2__ba_map_clear  ; 

  assign state0__ba_map_pre_act_rw  = ba_map_pre_act_rw  ;
  assign state0__ba_map_act_rw      = ba_map_act_rw      ;
  assign state0__ba_map_rw          = ba_map_rw          ;
  assign state0__ba_map_all_close   = ba_map_all_close   ;

  assign state1__ba_map_pre_act_rw  = ba_map_pre_act_rw  ;
  assign state1__ba_map_act_rw      = ba_map_act_rw      ;
  assign state1__ba_map_rw          = ba_map_rw          ;
  assign state1__ba_map_all_close   = ba_map_all_close   ;
                
  assign state2__ba_map_pre_act_rw  = ba_map_pre_act_rw  ;
  assign state2__ba_map_act_rw      = ba_map_act_rw      ;
  assign state2__ba_map_rw          = ba_map_rw          ;
  assign state2__ba_map_all_close   = ba_map_all_close   ;

  //-------------------------------------------------------------------------------------------------- 
  //
  //-------------------------------------------------------------------------------------------------- 
  hssdrc_decoder_state state0 (
    .clk               (clk  ),  
    .reset             (reset),
    .sclr              (sclr ),
    //
    .ba_map_update     (state0__ba_map_update    ),
    .ba_map_clear      (state0__ba_map_clear     ),
    .ba_map_pre_act_rw (state0__ba_map_pre_act_rw),
    .ba_map_act_rw     (state0__ba_map_act_rw    ),
    .ba_map_rw         (state0__ba_map_rw        ),
    .ba_map_all_close  (state0__ba_map_all_close ),
    //                 
    .arb_write         (arb0_write),
    .arb_read          (arb0_read ),
    .arb_refr          (arb0_refr ),
    .arb_rowa          (arb0_rowa ),
    .arb_cola          (arb0_cola ),
    .arb_ba            (arb0_ba   ),
    .arb_burst         (arb0_burst),
    .arb_chid          (arb0_chid ),
    .arb_ready         (arb0_ready),
    //                 
    .dec_pre_all       (dec0_pre_all),
    .dec_refr          (dec0_refr   ),
    .dec_pre           (dec0_pre    ),
    .dec_act           (dec0_act    ),
    .dec_read          (dec0_read   ),
    .dec_write         (dec0_write  ),
    //                 
    .dec_pre_all_enable(dec0_pre_all_enable),
    .dec_refr_enable   (dec0_refr_enable   ),
    .dec_pre_enable    (dec0_pre_enable    ),
    .dec_act_enable    (dec0_act_enable    ),
    .dec_read_enable   (dec0_read_enable   ),
    .dec_write_enable  (dec0_write_enable  ),
    //                 
    .dec_locked        (dec0_locked),
    .dec_last          (dec0_last  ),
    //                 
    .dec_rowa          (dec0_rowa ),
    .dec_cola          (dec0_cola ),
    .dec_ba            (dec0_ba   ),
    .dec_chid          (dec0_chid ),
    //                 
    .dec_burst         (dec0_burst) 
  ); 
  //-------------------------------------------------------------------------------------------------- 
  //
  //-------------------------------------------------------------------------------------------------- 
  hssdrc_decoder_state state1 (
    .clk               (clk  ),  
    .reset             (reset),
    .sclr              (sclr ),
    //
    .ba_map_update     (state1__ba_map_update    ),
    .ba_map_clear      (state1__ba_map_clear     ),
    .ba_map_pre_act_rw (state1__ba_map_pre_act_rw),
    .ba_map_act_rw     (state1__ba_map_act_rw    ),
    .ba_map_rw         (state1__ba_map_rw        ),
    .ba_map_all_close  (state1__ba_map_all_close ),
    //                 
    .arb_write         (arb1_write),
    .arb_read          (arb1_read ),
    .arb_refr          (arb1_refr ),
    .arb_rowa          (arb1_rowa ),
    .arb_cola          (arb1_cola ),
    .arb_ba            (arb1_ba   ),
    .arb_burst         (arb1_burst),
    .arb_chid          (arb1_chid ),
    .arb_ready         (arb1_ready),
    //                 
    .dec_pre_all       (dec1_pre_all),
    .dec_refr          (dec1_refr   ),
    .dec_pre           (dec1_pre    ),
    .dec_act           (dec1_act    ),
    .dec_read          (dec1_read   ),
    .dec_write         (dec1_write  ),
    //                 
    .dec_pre_all_enable(dec1_pre_all_enable),
    .dec_refr_enable   (dec1_refr_enable   ),
    .dec_pre_enable    (dec1_pre_enable    ),
    .dec_act_enable    (dec1_act_enable    ),
    .dec_read_enable   (dec1_read_enable   ),
    .dec_write_enable  (dec1_write_enable  ),
    //                 
    .dec_locked        (dec1_locked),
    .dec_last          (dec1_last  ),
    //                 
    .dec_rowa          (dec1_rowa ),
    .dec_cola          (dec1_cola ),
    .dec_ba            (dec1_ba   ),
    .dec_chid          (dec1_chid ),
    //                 
    .dec_burst         (dec1_burst)      
  ); 
  //-------------------------------------------------------------------------------------------------- 
  //
  //-------------------------------------------------------------------------------------------------- 
  hssdrc_decoder_state state2 (
    .clk               (clk  ),  
    .reset             (reset),
    .sclr              (sclr ), 
    //
    .ba_map_update     (state2__ba_map_update    ),
    .ba_map_clear      (state2__ba_map_clear     ),
    .ba_map_pre_act_rw (state2__ba_map_pre_act_rw),
    .ba_map_act_rw     (state2__ba_map_act_rw    ),
    .ba_map_rw         (state2__ba_map_rw        ),
    .ba_map_all_close  (state2__ba_map_all_close ),
    //                 
    .arb_write         (arb2_write),
    .arb_read          (arb2_read ),
    .arb_refr          (arb2_refr ),
    .arb_rowa          (arb2_rowa ),
    .arb_cola          (arb2_cola ),
    .arb_ba            (arb2_ba   ),
    .arb_burst         (arb2_burst),
    .arb_chid          (arb2_chid ),
    .arb_ready         (arb2_ready),
    //                 
    .dec_pre_all       (dec2_pre_all),
    .dec_refr          (dec2_refr   ),
    .dec_pre           (dec2_pre    ),
    .dec_act           (dec2_act    ),
    .dec_read          (dec2_read   ),
    .dec_write         (dec2_write  ),
    //                 
    .dec_pre_all_enable(dec2_pre_all_enable),
    .dec_refr_enable   (dec2_refr_enable   ),
    .dec_pre_enable    (dec2_pre_enable    ),
    .dec_act_enable    (dec2_act_enable    ),
    .dec_read_enable   (dec2_read_enable   ),
    .dec_write_enable  (dec2_write_enable  ),
    //                 
    .dec_locked        (dec2_locked),
    .dec_last          (dec2_last  ),
    //                 
    .dec_rowa          (dec2_rowa ),
    .dec_cola          (dec2_cola ),
    .dec_ba            (dec2_ba   ),
    .dec_chid          (dec2_chid ),
    //                 
    .dec_burst         (dec2_burst) 
  ); 

endmodule