data_gen_translate.vhd

In communication systems channel poses an important role. channels can convolve many different kind

  channel_tap2_madd_add_out_inst_cy_3_11 : X_MUX2
    port map (
      IA => channel_tap1_dout(7),
      IB => channel_tap2_madd_add_out_inst_cy_2,
      SEL => channel_tap2_madd_add_out_inst_lut2_3,
      O => channel_tap2_madd_add_out_inst_cy_3
    );
  channel_tap2_dout_7 : X_FF
    port map (
      I => channel_tap1_dout(7),
      CLK => clock_bufgp,
      O => channel_tap2_dout(7),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  channel_tap2_madd_add_out_inst_sum_5 : X_XOR2
    port map (
      I0 => channel_tap2_madd_add_out_inst_cy_4,
      I1 => n2175,
      O => channel_t_res_out2(5)
    );
  dxout_6_obuf : X_BUF
    port map (
      I => channel_tap3_dout(7),
      O => dxout_6_obuf_GTS_TRI
    );
  dxout_3_obuf : X_BUF
    port map (
      I => channel_tap3_dout(7),
      O => dxout_3_obuf_GTS_TRI
    );
  dxout_2_obuf : X_BUF
    port map (
      I => channel_tap3_dout(7),
      O => dxout_2_obuf_GTS_TRI
    );
  xout_3_obuf_12 : X_BUF
    port map (
      I => xout_3_obuf,
      O => xout_3_obuf_GTS_TRI
    );
  channel_tap3_madd_add_out_inst_sum_2 : X_XOR2
    port map (
      I0 => channel_tap3_madd_add_out_inst_cy_1,
      I1 => channel_tap3_madd_add_out_inst_lut2_2,
      O => xout_2_obuf
    );
  channel_tap3_madd_add_out_inst_cy_2_13 : X_MUX2
    port map (
      IA => channel_t_res_out2(2),
      IB => channel_tap3_madd_add_out_inst_cy_1,
      SEL => channel_tap3_madd_add_out_inst_lut2_2,
      O => channel_tap3_madd_add_out_inst_cy_2
    );
  channel_tap3_madd_add_out_inst_sum_4 : X_XOR2
    port map (
      I0 => channel_tap3_madd_add_out_inst_cy_3,
      I1 => channel_tap3_madd_add_out_inst_lut2_4,
      O => xout_4_obuf
    );
  channel_tap2_madd_add_out_inst_lut2_21 : X_LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      ADR0 => channel_tap2_mul_res(2),
      ADR1 => data_7_Q,
      O => channel_tap2_madd_add_out_inst_lut2_2
    );
  channel_tap2_mmux_mul_res_i5_result1 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => channel_tap1_dout(7),
      O => channel_tap2_mul_res(2),
      ADR1 => GND
    );
  channel_tap3_madd_add_out_inst_cy_4_14 : X_MUX2
    port map (
      IA => channel_t_res_out2(4),
      IB => channel_tap3_madd_add_out_inst_cy_3,
      SEL => channel_tap3_madd_add_out_inst_lut2_4,
      O => channel_tap3_madd_add_out_inst_cy_4
    );
  channel_tap3_madd_add_out_inst_lut2_31 : X_LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      ADR0 => channel_t_res_out2(3),
      ADR1 => channel_tap2_dout(7),
      O => channel_tap3_madd_add_out_inst_lut2_3
    );
  channel_tap2_madd_add_out_inst_sum_3 : X_XOR2
    port map (
      I0 => channel_tap2_madd_add_out_inst_cy_2,
      I1 => channel_tap2_madd_add_out_inst_lut2_3,
      O => channel_t_res_out2(3)
    );
  channel_tap3_madd_add_out_inst_lut2_51 : X_LUT2
    generic map(
      INIT => X"9"
    )
    port map (
      ADR0 => channel_t_res_out2(5),
      ADR1 => channel_tap2_dout(7),
      O => channel_tap3_madd_add_out_inst_lut2_5
    );
  xout_6_obuf_15 : X_BUF
    port map (
      I => xout_6_obuf,
      O => xout_6_obuf_GTS_TRI
    );
  channel_tap3_madd_add_out_inst_sum_3 : X_XOR2
    port map (
      I0 => channel_tap3_madd_add_out_inst_cy_2,
      I1 => channel_tap3_madd_add_out_inst_lut2_3,
      O => xout_3_obuf
    );
  channel_tap1_dout_7 : X_FF
    port map (
      I => data_7_Q,
      CLK => clock_bufgp,
      O => channel_tap1_dout(7),
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  channel_tap2_madd_add_out_inst_lut2_61 : X_LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      ADR0 => channel_tap2_mul_res(2),
      ADR1 => data_7_Q,
      O => channel_tap2_madd_add_out_inst_lut2_6
    );
  dxout_7_obuf : X_BUF
    port map (
      I => channel_tap3_dout(7),
      O => dxout_7_obuf_GTS_TRI
    );
  xout_2_obuf_16 : X_BUF
    port map (
      I => xout_2_obuf,
      O => xout_2_obuf_GTS_TRI
    );
  xout_4_obuf_17 : X_BUF
    port map (
      I => xout_4_obuf,
      O => xout_4_obuf_GTS_TRI
    );
  channel_tap2_madd_add_out_inst_sum_7 : X_XOR2
    port map (
      I0 => channel_tap2_madd_add_out_inst_cy_6,
      I1 => channel_tap2_madd_add_out_inst_lut2_5,
      O => channel_t_res_out2(7)
    );
  channel_tap2_madd_add_out_inst_cy_4_18 : X_MUX2
    port map (
      IA => channel_tap1_dout(7),
      IB => channel_tap2_madd_add_out_inst_cy_3,
      SEL => channel_tap2_madd_add_out_inst_lut2_4,
      O => channel_tap2_madd_add_out_inst_cy_4
    );
  channel_tap2_madd_add_out_inst_sum_2 : X_XOR2
    port map (
      I0 => channel_tap2_madd_add_out_inst_cy_1,
      I1 => channel_tap2_madd_add_out_inst_lut2_2,
      O => channel_t_res_out2(2)
    );
  channel_tap3_madd_add_out_inst_cy_3_19 : X_MUX2
    port map (
      IA => channel_t_res_out2(3),
      IB => channel_tap3_madd_add_out_inst_cy_2,
      SEL => channel_tap3_madd_add_out_inst_lut2_3,
      O => channel_tap3_madd_add_out_inst_cy_3
    );
  dxout_1_obuf : X_BUF
    port map (
      I => channel_tap3_dout(7),
      O => dxout_1_obuf_GTS_TRI
    );
  channel_tap3_madd_add_out_inst_sum_7 : X_XOR2
    port map (
      I0 => channel_tap3_madd_add_out_inst_cy_6,
      I1 => channel_tap3_madd_add_out_inst_lut2_7,
      O => xout_7_obuf
    );
  channel_tap3_madd_add_out_inst_lut2_11 : X_LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      ADR0 => channel_tap2_dout(7),
      ADR1 => data_7_Q,
      O => channel_tap3_madd_add_out_inst_lut2_1
    );
  Q_n0003_22 : X_LUT2
    generic map(
      INIT => X"5"
    )
    port map (
      ADR0 => data_7_Q,
      ADR1 => GND,
      O => Q_n0003_O
    );
  Q_n0003_LUT1_L_BUF : X_BUF
    port map (
      I => Q_n0003_O,
      O => Q_n0003
    );
  clock_bufgp_IBUFG_23 : X_CKBUF
    port map (
      I => clock,
      O => clock_bufgp_IBUFG
    );
  clock_bufgp_BUFG : X_CKBUF
    port map (
      I => clock_bufgp_IBUFG,
      O => clock_bufgp
    );
  dxout_7_obuf_GTS_TRI_24 : X_TRI
    port map (
      I => dxout_7_obuf_GTS_TRI,
      CTL => NlwInverterSignal_dxout_7_obuf_GTS_TRI_CTL,
      O => dxout(7)
    );
  dxout_6_obuf_GTS_TRI_25 : X_TRI
    port map (
      I => dxout_6_obuf_GTS_TRI,
      CTL => NlwInverterSignal_dxout_6_obuf_GTS_TRI_CTL,
      O => dxout(6)
    );
  dxout_5_obuf_GTS_TRI_26 : X_TRI
    port map (
      I => dxout_5_obuf_GTS_TRI,
      CTL => NlwInverterSignal_dxout_5_obuf_GTS_TRI_CTL,
      O => dxout(5)
    );
  dxout_4_obuf_GTS_TRI_27 : X_TRI
    port map (
      I => dxout_4_obuf_GTS_TRI,
      CTL => NlwInverterSignal_dxout_4_obuf_GTS_TRI_CTL,
      O => dxout(4)
    );
  dxout_3_obuf_GTS_TRI_28 : X_TRI
    port map (
      I => dxout_3_obuf_GTS_TRI,
      CTL => NlwInverterSignal_dxout_3_obuf_GTS_TRI_CTL,
      O => dxout(3)
    );
  dxout_2_obuf_GTS_TRI_29 : X_TRI
    port map (
      I => dxout_2_obuf_GTS_TRI,
      CTL => NlwInverterSignal_dxout_2_obuf_GTS_TRI_CTL,
      O => dxout(2)
    );
  dxout_1_obuf_GTS_TRI_30 : X_TRI
    port map (
      I => dxout_1_obuf_GTS_TRI,
      CTL => NlwInverterSignal_dxout_1_obuf_GTS_TRI_CTL,
      O => dxout(1)
    );
  dxout_0_obuf_GTS_TRI_31 : X_TRI
    port map (
      I => dxout_0_obuf_GTS_TRI,
      CTL => NlwInverterSignal_dxout_0_obuf_GTS_TRI_CTL,
      O => dxout(0)
    );
  xout_7_obuf_GTS_TRI_32 : X_TRI
    port map (
      I => xout_7_obuf_GTS_TRI,
      CTL => NlwInverterSignal_xout_7_obuf_GTS_TRI_CTL,
      O => xout(7)
    );
  xout_6_obuf_GTS_TRI_33 : X_TRI
    port map (
      I => xout_6_obuf_GTS_TRI,
      CTL => NlwInverterSignal_xout_6_obuf_GTS_TRI_CTL,
      O => xout(6)
    );
  xout_5_obuf_GTS_TRI_34 : X_TRI
    port map (
      I => xout_5_obuf_GTS_TRI,
      CTL => NlwInverterSignal_xout_5_obuf_GTS_TRI_CTL,
      O => xout(5)
    );
  xout_4_obuf_GTS_TRI_35 : X_TRI
    port map (
      I => xout_4_obuf_GTS_TRI,
      CTL => NlwInverterSignal_xout_4_obuf_GTS_TRI_CTL,
      O => xout(4)
    );
  xout_3_obuf_GTS_TRI_36 : X_TRI
    port map (
      I => xout_3_obuf_GTS_TRI,
      CTL => NlwInverterSignal_xout_3_obuf_GTS_TRI_CTL,
      O => xout(3)
    );
  xout_2_obuf_GTS_TRI_37 : X_TRI
    port map (
      I => xout_2_obuf_GTS_TRI,
      CTL => NlwInverterSignal_xout_2_obuf_GTS_TRI_CTL,
      O => xout(2)
    );
  xout_1_obuf_GTS_TRI_38 : X_TRI
    port map (
      I => xout_1_obuf_GTS_TRI,
      CTL => NlwInverterSignal_xout_1_obuf_GTS_TRI_CTL,
      O => xout(1)
    );
  xout_0_obuf_GTS_TRI_39 : X_TRI
    port map (
      I => xout_0_obuf_GTS_TRI,
      CTL => NlwInverterSignal_xout_0_obuf_GTS_TRI_CTL,
      O => xout(0)
    );
  NlwBlock_data_gen_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_data_gen_GND : X_ZERO
    port map (
      O => GND
    );
  NlwInverterBlock_dxout_7_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_dxout_7_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_dxout_6_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_dxout_6_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_dxout_5_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_dxout_5_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_dxout_4_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_dxout_4_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_dxout_3_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_dxout_3_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_dxout_2_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_dxout_2_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_dxout_1_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_dxout_1_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_dxout_0_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_dxout_0_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_xout_7_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_xout_7_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_xout_6_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_xout_6_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_xout_5_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_xout_5_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_xout_4_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_xout_4_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_xout_3_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_xout_3_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_xout_2_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_xout_2_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_xout_1_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_xout_1_obuf_GTS_TRI_CTL
    );
  NlwInverterBlock_xout_0_obuf_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_xout_0_obuf_GTS_TRI_CTL
    );
  NlwBlockROC : ROC generic map ( WIDTH => 100 ns)
     port map (O => GSR);
  NlwBlockTOC : TOC     port map (O => GTS);
end Structure;