📄 test_lms.vhd

📁 In communication systems channel poses an important role. channels can convolve many different kind
💻 VHD
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"01000000","11000000"		);	  CONSTANT filter_x_in : filter_data :=	    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tf_lms PORT MAP(		xin => xin,		dxin => dxin,		clock => clock,		err => err,     	adapt_en => adapt_en,		 		yout => yout	);-- *** Test Bench - User Defined Section ***   clk_gen: PROCESS   BEGIN	    clock <= '1';	    WAIT FOR clk_high;	    clock <= '0';	    WAIT FOR clk_low;   END PROCESS clk_gen;   tb:   PROCESS    		variable IN_x,IN_dx:std_logic_vector(7 downto 0); 		VARIABLE TX_STR : String(1 to 512);		VARIABLE TX_LOC : LINE;		VARIABLE RX_LOC : LINE;     BEGIN					    				   		adapt_en <= '1';		FOR n IN 0 TO 500 LOOP--			readline(F_XIN,xin);			--xin <= IN_X;			--Deallocate(RX_LOC);			xin  <= filter_x_in(n);	   		dxin <= filter_dx_in(n);			wait for clk_period;			write(TX_LOC,string'("'"));			write(TX_LOC, yout);				write(TX_LOC,string'("'"));			writeline(results, TX_LOC);			Deallocate(TX_LOC);			write(TX_LOC,string'("'"));			write(TX_LOC, err);				write(TX_LOC,string'("'"));			writeline(ERRF, TX_LOC);			Deallocate(TX_LOC);		end loop;	--	adapt_en <= '0';		FOR n IN 501 TO 999 LOOP--			readline(F_XIN,xin);			--xin <= IN_X;			--Deallocate(RX_LOC);			xin  <= filter_x_in(n);	   		dxin <= filter_dx_in(n);			wait for clk_period;			write(TX_LOC,string'("'"));			write(TX_LOC, yout);				write(TX_LOC,string'("'"));			writeline(results, TX_LOC);			Deallocate(TX_LOC);			write(TX_LOC,string'("'"));			write(TX_LOC, err);				write(TX_LOC,string'("'"));			writeline(ERRF, TX_LOC);			Deallocate(TX_LOC);		end loop;		   wait; -- will wait forever   END PROCESS;-- *** End Test Bench - User Defined Section ***END;
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💿 文件大小 14 K
👤 上传用户 huajunun
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#communication #important #different #channels
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