twofish.vhd

VHDL implementation of the twofish cipher for 128,192 and 256 bit keys. The implementation is in li

	m11_with_f3: mulf3
	port map	(
				in_mulf3 => m11,
				out_mulf3 => m11_f3
				);

	m12_with_1e: mul1e
	port map	(
				in_mul1e => m12,
				out_mul1e => m12_1e
				);

	m13_with_c6: mulc6
	port map	(
				in_mulc6 => m13,
				out_mulc6 => m13_c6
				);

	m14_with_68: mul68
	port map	(
				in_mul68 => m14,
				out_mul68 => m14_68
				);

	m15_with_e5: mule5
	port map	(
				in_mule5 => m15,
				out_mule5 => m15_e5
				);

	-- the third row creates s12
	m8_with_02: mul02
	port map	(
				in_mul02 => m8,
				out_mul02 => m8_02
				);

	m9_with_a1: mula1
	port map	(
				in_mula1 => m9,
				out_mula1 => m9_a1
				);

	m10_with_fc: mulfc
	port map	(
				in_mulfc => m10,
				out_mulfc => m10_fc
				);

	m11_with_c1: mulc1
	port map	(
				in_mulc1 => m11,
				out_mulc1 => m11_c1
				);

	m12_with_47: mul47
	port map	(
				in_mul47 => m12,
				out_mul47 => m12_47
				);

	m13_with_ae: mulae
	port map	(
				in_mulae => m13,
				out_mulae => m13_ae
				);

	m14_with_3d: mul3d
	port map	(
				in_mul3d => m14,
				out_mul3d => m14_3d
				);

	m15_with_19: mul19
	port map	(
				in_mul19 => m15,
				out_mul19 => m15_19
				);

	-- the fourth row creates s13
	m8_with_a4_1: mula4
	port map	(
				in_mula4 => m8,
				out_mula4 => m8_a4_1
				);

	m9_with_55: mul55
	port map	(
				in_mul55 => m9,
				out_mul55 => m9_55
				);

	m10_with_87: mul87
	port map	(
				in_mul87 => m10,
				out_mul87 => m10_87
				);

	m11_with_5a: mul5a
	port map	(
				in_mul5a => m11,
				out_mul5a => m11_5a
				);

	m12_with_58: mul58
	port map	(
				in_mul58 => m12,
				out_mul58 => m12_58
				);

	m13_with_db: muldb
	port map	(
				in_muldb => m13,
				out_muldb => m13_db
				);

	m14_with_9e: mul9e
	port map	(
				in_mul9e => m14,
				out_mul9e => m14_9e
				);

	m15_with_03: mul03
	port map	(
				in_mul03 => m15,
				out_mul03 => m15_03
				);


	-- after getting the results from multipliers
	-- we combine them in order to get the additions
	s00 <= m0_01 XOR m1_a4 XOR m2_55 XOR m3_87 XOR m4_5a XOR m5_58 XOR m6_db XOR m7_9e;
	s01 <= m0_a4 XOR m1_56 XOR m2_82 XOR m3_f3 XOR m4_1e XOR m5_c6 XOR m6_68 XOR m7_e5;
	s02 <= m0_02 XOR m1_a1 XOR m2_fc XOR m3_c1 XOR m4_47 XOR m5_ae XOR m6_3d XOR m7_19;
	s03 <= m0_a4_1 XOR m1_55 XOR m2_87 XOR m3_5a XOR m4_58 XOR m5_db XOR m6_9e XOR m7_03;

	-- after creating s0,j j=0...3 we form the S0
	-- little endian 
	out_Sfirst_rs128 <= s03 & s02 & s01 & s00;

	s10 <= m8_01 XOR m9_a4 XOR m10_55 XOR m11_87 XOR m12_5a XOR m13_58 XOR m14_db XOR m15_9e;
	s11 <= m8_a4 XOR m9_56 XOR m10_82 XOR m11_f3 XOR m12_1e XOR m13_c6 XOR m14_68 XOR m15_e5;
	s12 <= m8_02 XOR m9_a1 XOR m10_fc XOR m11_c1 XOR m12_47 XOR m13_ae XOR m14_3d XOR m15_19;
	s13 <= m8_a4_1 XOR m9_55 XOR m10_87 XOR m11_5a XOR m12_58 XOR m13_db XOR m14_9e XOR m15_03;

	-- after creating s1,j j=0...3 we form the S1
	-- little endian
	out_Ssecond_rs128 <= s13 & s12 & s11 & s10;

end rs_128_arch;

-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--																			--
-- 								new component								--
--																			--
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --

--
-- h function for 128 bits key
-- 

library ieee;
use ieee.std_logic_1164.all;

entity h_128 is
port	(
		in_h128		: in std_logic_vector(7 downto 0);
		Mfirst_h128,
		Msecond_h128	: in std_logic_vector(31 downto 0);
		out_h128		: out std_logic_vector(31 downto 0)
		);
end h_128;

architecture h128_arch of h_128 is

	-- we declare internal signals
	signal	from_first_row,
			to_second_row,
			from_second_row,
			to_third_row,
			to_mds			: std_logic_vector(31 downto 0);
					
	-- we declare all components needed 				   
	component q0
	port	(			   
			in_q0 	: in std_logic_vector(7 downto 0);
			out_q0	: out std_logic_vector(7 downto 0)
			);
	end component;
	
	component q1
	port	(
			in_q1 	: in std_logic_vector(7 downto 0);
			out_q1	: out std_logic_vector(7 downto 0)
			);
	end component;

	component mds
	port	(
			y0,
			y1,
			y2,
			y3	: in std_logic_vector(7 downto 0);
			z0,
			z1,
			z2,
			z3	: out std_logic_vector(7 downto 0)
			);
	end component;

-- begin architecture description
begin

	-- first row of q
	first_q0_1: q0
	port map	(
				in_q0 => in_h128,
				out_q0 => from_first_row(7 downto 0)
				);
	first_q1_1: q1
	port map	(
				in_q1 => in_h128,
				out_q1 => from_first_row(15 downto 8)
				);
	first_q0_2: q0
	port map	(
				in_q0 => in_h128,
				out_q0 => from_first_row(23 downto 16)
				);
	first_q1_2: q1
	port map	(
				in_q1 => in_h128,
				out_q1 => from_first_row(31 downto 24)
				);

	-- we perform the XOR of the results of the first row
	-- with first M of h (Mfist_h128)
	to_second_row <= from_first_row XOR Mfirst_h128;

	-- second row of q
	second_q0_1: q0
	port map	(
				in_q0 => to_second_row(7 downto 0),
				out_q0 => from_second_row(7 downto 0)
				);
	second_q0_2: q0
	port map	(
				in_q0 => to_second_row(15 downto 8),
				out_q0 => from_second_row(15 downto 8)
				);
	second_q1_1: q1
	port map	(
				in_q1 => to_second_row(23 downto 16),
				out_q1 => from_second_row(23 downto 16)
				);
	second_q1_2: q1
	port map	(
				in_q1 => to_second_row(31 downto 24),
				out_q1 => from_second_row(31 downto 24)
				);
				
	-- we perform the second XOR
	to_third_row <= from_second_row XOR Msecond_h128;
	
	-- the third row of q
	third_q1_1: q1
	port map	(
				in_q1 => to_third_row(7 downto 0),
				out_q1 => to_mds(7 downto 0)
				);
	third_q0_1: q0
	port map	(
				in_q0 => to_third_row(15 downto 8),
				out_q0 => to_mds(15 downto 8)
				);
	third_q1_2: q1
	port map	(
				in_q1 => to_third_row(23 downto 16),
				out_q1 => to_mds(23 downto 16)
				);
	third_q0_2: q0
	port map	(
				in_q0 => to_third_row(31 downto 24),
				out_q0 => to_mds(31 downto 24)
				);
				
	-- mds table
	mds_table: mds
	port map	(
				y0 => to_mds(7 downto 0),
				y1 => to_mds(15 downto 8),
				y2 => to_mds(23 downto 16),
				y3 => to_mds(31 downto 24),
				z0 => out_h128(7 downto 0),
				z1 => out_h128(15 downto 8),
				z2 => out_h128(23 downto 16),
				z3 => out_h128(31 downto 24)
				);

end h128_arch;


-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--																			--
-- 								new component								--
--																			--
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --


--
-- g function for 128 bits key
-- 

library ieee;
use ieee.std_logic_1164.all;

entity g_128 is
port	(
		in_g128,
		in_S0_g128,
		in_S1_g128		: in std_logic_vector(31 downto 0);
		out_g128		: out std_logic_vector(31 downto 0)
		);
end g_128;

architecture g128_arch of g_128 is

	-- we declare the internal signals
	signal	from_first_row,
			to_second_row,
			from_second_row,
			to_third_row,
			to_mds			: std_logic_vector(31 downto 0);

	component q0
	port	(
			in_q0 	: in std_logic_vector(7 downto 0);
			out_q0	: out std_logic_vector(7 downto 0)
			);
	end component;
	
	component q1
	port	(
			in_q1 	: in std_logic_vector(7 downto 0);
			out_q1	: out std_logic_vector(7 downto 0)
			);
	end component;

	component mds
	port	(
			y0,
			y1,
			y2,
			y3	: in std_logic_vector(7 downto 0);
			z0,
			z1,
			z2,
			z3	: out std_logic_vector(7 downto 0)
			);
	end component;

-- begin architecture description
begin

	-- first row of q
	first_q0_1: q0
	port map	(
				in_q0 => in_g128(7 downto 0),
				out_q0 => from_first_row(7 downto 0)
				);
	first_q1_1: q1
	port map	(
				in_q1 => in_g128(15 downto 8),
				out_q1 => from_first_row(15 downto 8)
				);
	first_q0_2: q0
	port map	(
				in_q0 => in_g128(23 downto 16),
				out_q0 => from_first_row(23 downto 16)
				);
	first_q1_2: q1
	port map	(
				in_q1 => in_g128(31 downto 24),
				out_q1 => from_first_row(31 downto 24)
				);

	-- we XOR the result of the first row
	-- with the S0
	to_second_row <= from_first_row XOR in_S0_g128;

	-- second row of q
	second_q0_1: q0
	port map	(
				in_q0 => to_second_row(7 downto 0),
				out_q0 => from_second_row(7 downto 0)
				);
	second_q0_2: q0
	port map	(
				in_q0 => to_second_row(15 downto 8),
				out_q0 => from_second_row(15 downto 8)
				);
	second_q1_1: q1
	port map	(
				in_q1 => to_second_row(23 downto 16),
				out_q1 => from_second_row(23 downto 16)
				);
	second_q1_2: q1
	port map	(
				in_q1 => to_second_row(31 downto 24),
				out_q1 => from_second_row(31 downto 24)
				);
				
	-- we perform the XOR
	to_third_row <= from_second_row XOR in_S1_g128;
	
	-- third row of q
	third_q1_1: q1
	port map	(
				in_q1 => to_third_row(7 downto 0),
				out_q1 => to_mds(7 downto 0)
				);
	third_q0_1: q0
	port map	(
				in_q0 => to_third_row(15 downto 8),
				out_q0 => to_mds(15 downto 8)
				);
	third_q1_2: q1
	port map	(
				in_q1 => to_third_row(23 downto 16),
				out_q1 => to_mds(23 downto 16)
				);
	third_q0_2: q0
	port map	(
				in_q0 => to_third_row(31 downto 24),
				out_q0 => to_mds(31 downto 24)
				);
				
	-- mds table 
	mds_table: mds
	port map	(
				y0 => to_mds(7 downto 0),
				y1 => to_mds(15 downto 8),
				y2 => to_mds(23 downto 16),
				y3 => to_mds(31 downto 24),
				z0 => out_g128(7 downto 0),
				z1 => out_g128(15 downto 8),
				z2 => out_g128(23 downto 16),
				z3 => out_g128(31 downto 24)
				);

end g128_arch;


-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --
--																			--
-- 								new component								--
--																			--
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --


--
-- f function with 128 bits key
-- 

library ieee;
use ieee.std_logic_1164.all;

entity f_128 is
port	(
		up_in_f128,
		low_in_f128,
		S0_in_f128,
		S1_in_f128,
		up_key_f128,
		low_key_f128		: in std_logic_vector(31 downto 0);
		up_out_f128,
		low_out_f128		: out std_logic_vector(31 downto 0)
		);
end f_128;

architecture f128_arch of f_128 is

	-- we declare the internal signals 
	signal	from_shift_8,
			to_up_pht,
			to_low_pht,
			to_up_key,
			to_low_key,
			intermediate_carry1,
			intermediate_carry2	: std_logic_vector(31 downto 0);
	signal	zero					: std_logic;
	
	
	component g_128
	port	(
			in_g128,
			in_S0_g128,
			in_S1_g128	: in std_logic_vector(31 downto 0);
			out_g128		: out std_logic_vector(31 downto 0)
			);
	end component;
	
	component pht
	port	(
			up_in_pht,
			down_in_pht	: in std_logic_vector(31 downto 0);
			up_out_pht,
			down_out_pht	: out std_logic_vector(31 downto 0)
			);
	end component;

	component adder
	port	(
			in1_adder,
			in2_adder,
			in_carry_adder	: in std_logic;
			out_adder,
			out_carry_adder	: out std_logic
			);
	end component;

-- begin architecture description
begin

	-- we initialize zero
	zero <= '0';
	
	-- upper g_128
	upper_g128: g_128
	port map	(
				in_g128 => up_in