twofish.vhd

来自「VHDL implementation of the twofish ciphe」· VHDL 代码 · 共 2,663 行 · 第 1/5 页

library ieee;
use ieee.std_logic_1164.all;

entity reed_solomon128 is
port	(
		in_rs128			: in std_logic_vector(127 downto 0);
		out_Sfirst_rs128,
		out_Ssecond_rs128		: out std_logic_vector(31 downto 0)	
		);
end reed_solomon128;

architecture rs_128_arch of reed_solomon128 is

	-- declaring all components necessary for reed solomon
	-- 01
	component mul01
	port	(
			in_mul01	: in std_logic_vector(7 downto 0);
			out_mul01	: out std_logic_vector(7 downto 0)
			);
	end component;

	-- a4	
	component mula4 
	port	(
			in_mula4	: in std_logic_vector(7 downto 0);			
			out_mula4	: out std_logic_vector(7 downto 0)
			);
	end component;

	-- 55
	component mul55 
	port	(
			in_mul55	: in std_logic_vector(7 downto 0);
			out_mul55	: out std_logic_vector(7 downto 0)
			);
	end component;

	-- 87
	component mul87 
	port	(
			in_mul87	: in std_logic_vector(7 downto 0);
			out_mul87	: out std_logic_vector(7 downto 0)
			);
	end component;

	-- 5a
	component mul5a 
	port	(
			in_mul5a	: in std_logic_vector(7 downto 0);
			out_mul5a	: out std_logic_vector(7 downto 0)
			);
	end component;

	-- 58
	component mul58 
	port	(
			in_mul58	: in std_logic_vector(7 downto 0);
			out_mul58	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- db
	component muldb 
	port	(
			in_muldb	: in std_logic_vector(7 downto 0);
			out_muldb	: out std_logic_vector(7 downto 0)
			);
	end component;

	
	-- 9e
	component mul9e 
	port	(
			in_mul9e	: in std_logic_vector(7 downto 0);
			out_mul9e	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- 56
	component mul56 
	port	(
			in_mul56	: in std_logic_vector(7 downto 0);
			out_mul56	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- 82
	component mul82 
	port	(
			in_mul82	: in std_logic_vector(7 downto 0);
			out_mul82	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- f3
	component mulf3 
	port	(
			in_mulf3	: in std_logic_vector(7 downto 0);
			out_mulf3	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- 1e
	component mul1e 
	port	(
			in_mul1e	: in std_logic_vector(7 downto 0);
			out_mul1e	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- c6
	component mulc6 
	port	(
			in_mulc6	: in std_logic_vector(7 downto 0);
			out_mulc6	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- 68
	component mul68 
	port	(
			in_mul68	: in std_logic_vector(7 downto 0);
			out_mul68	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- e5
	component mule5 
	port	(
			in_mule5	: in std_logic_vector(7 downto 0);
			out_mule5	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- 02
	component mul02 
	port	(
			in_mul02	: in std_logic_vector(7 downto 0);
			out_mul02	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- a1
	component mula1 
	port	(
			in_mula1	: in std_logic_vector(7 downto 0);
			out_mula1	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- fc
	component mulfc 
	port	(
			in_mulfc	: in std_logic_vector(7 downto 0);
			out_mulfc	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- c1
	component mulc1 
	port	(
			in_mulc1	: in std_logic_vector(7 downto 0);
			out_mulc1	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- 47
	component mul47 
	port	(
			in_mul47	: in std_logic_vector(7 downto 0);
			out_mul47	: out std_logic_vector(7 downto 0)	
			);
	end component;



	-- ae
	component mulae 
	port	(
			in_mulae	: in std_logic_vector(7 downto 0);
			out_mulae	: out std_logic_vector(7 downto 0)
			);
	end component;



	-- 3d
	component mul3d 
	port	(
			in_mul3d	: in std_logic_vector(7 downto 0);
			out_mul3d	: out std_logic_vector(7 downto 0)
			);
	end component;



	-- 19
	component mul19 
	port	(
			in_mul19	: in std_logic_vector(7 downto 0);
			out_mul19	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- 03
	component mul03 
	port	(
			in_mul03	: in std_logic_vector(7 downto 0);
			out_mul03	: out std_logic_vector(7 downto 0)
			);
	end component;


	-- declaring internal signals
	signal	m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,m11,m12,m13,m14,m15		: std_logic_vector(7 downto 0);	
	signal 	s00,s01,s02,s03,s10,s11,s12,s13								: std_logic_vector(7 downto 0);	
	signal	m0_01,m1_a4,m2_55,m3_87,m4_5a,m5_58,m6_db,m7_9e,
			m0_a4,m1_56,m2_82,m3_f3,m4_1e,m5_c6,m6_68,m7_e5,
			m0_02,m1_a1,m2_fc,m3_c1,m4_47,m5_ae,m6_3d,m7_19,
			m0_a4_1,m1_55,m2_87,m3_5a,m4_58,m5_db,m6_9e,m7_03			: std_logic_vector(7 downto 0);	
	signal	m8_01,m9_a4,m10_55,m11_87,m12_5a,m13_58,m14_db,m15_9e,
			m8_a4,m9_56,m10_82,m11_f3,m12_1e,m13_c6,m14_68,m15_e5,
			m8_02,m9_a1,m10_fc,m11_c1,m12_47,m13_ae,m14_3d,m15_19,
			m8_a4_1,m9_55,m10_87,m11_5a,m12_58,m13_db,m14_9e,m15_03		: std_logic_vector(7 downto 0);	

-- begin architecture description
begin

	-- first, we separate the input to the respective m
	-- for s1,j j=0..3
	m0 <= in_rs128(7 downto 0);
	m1 <= in_rs128(15 downto 8);
	m2 <= in_rs128(23 downto 16);
	m3 <= in_rs128(31 downto 24);
	m4 <= in_rs128(39 downto 32);
	m5 <= in_rs128(47 downto 40);
	m6 <= in_rs128(55 downto 48);
	m7 <= in_rs128(63 downto 56);

	-- for s0,j j=0..3
	m8 <= in_rs128(71 downto 64);
	m9 <= in_rs128(79 downto 72);
	m10 <= in_rs128(87 downto 80);
	m11 <= in_rs128(95 downto 88);
	m12 <= in_rs128(103 downto 96);
	m13 <= in_rs128(111 downto 104);
	m14 <= in_rs128(119 downto 112);
	m15 <= in_rs128(127 downto 120);


	-- after separating signals, we drive them to multipliers
	-- the first line of m0..7 forms s00
	m0_with_01: mul01
	port map	(
				in_mul01 => m0,
				out_mul01 => m0_01
				);

	m1_with_a4: mula4
	port map	(
				in_mula4 => m1,
				out_mula4 => m1_a4
				);

	m2_with_55: mul55
	port map	(
				in_mul55 => m2,
				out_mul55 => m2_55
				);

	m3_with_87: mul87
	port map	(
				in_mul87 => m3,
				out_mul87 => m3_87
				);

	m4_with_5a: mul5a
	port map	(
				in_mul5a => m4,
				out_mul5a => m4_5a
				);

	m5_with_58: mul58
	port map	(
				in_mul58 => m5,
				out_mul58 => m5_58
				);

	m6_with_db: muldb
	port map	(
				in_muldb => m6,
				out_muldb => m6_db
				);

	m7_with_9e: mul9e
	port map	(
				in_mul9e => m7,
				out_mul9e => m7_9e
				);

	-- the second row creates s01
	m0_with_a4: mula4
	port map	(
				in_mula4 => m0,
				out_mula4 => m0_a4
				);

	m1_with_56: mul56
	port map	(
				in_mul56 => m1,
				out_mul56 => m1_56
				);

	m2_with_82: mul82
	port map	(
				in_mul82 => m2,
				out_mul82 => m2_82
				);
	
	m3_with_f3: mulf3
	port map	(
				in_mulf3 => m3,
				out_mulf3 => m3_f3
				);

	m4_with_1e: mul1e
	port map	(
				in_mul1e => m4,
				out_mul1e => m4_1e
				);

	m5_with_c6: mulc6
	port map	(
				in_mulc6 => m5,
				out_mulc6 => m5_c6
				);

	m6_with_68: mul68
	port map	(
				in_mul68 => m6,
				out_mul68 => m6_68
				);

	m7_with_e5: mule5
	port map	(
				in_mule5 => m7,
				out_mule5 => m7_e5
				);

	-- the third row creates s02
	m0_with_02: mul02
	port map	(
				in_mul02 => m0,
				out_mul02 => m0_02
				);

	m1_with_a1: mula1
	port map	(
				in_mula1 => m1,
				out_mula1 => m1_a1
				);

	m2_with_fc: mulfc
	port map	(
				in_mulfc => m2,
				out_mulfc => m2_fc
				);

	m3_with_c1: mulc1
	port map	(
				in_mulc1 => m3,
				out_mulc1 => m3_c1
				);

	m4_with_47: mul47
	port map	(
				in_mul47 => m4,
				out_mul47 => m4_47
				);

	m5_with_ae: mulae
	port map	(
				in_mulae => m5,
				out_mulae => m5_ae
				);

	m6_with_3d: mul3d
	port map	(
				in_mul3d => m6,
				out_mul3d => m6_3d
				);

	m7_with_19: mul19
	port map	(
				in_mul19 => m7,
				out_mul19 => m7_19
				);

	-- the fourth row creates s03
	m0_with_a4_1: mula4
	port map	(
				in_mula4 => m0,
				out_mula4 => m0_a4_1
				);

	m1_with_55: mul55
	port map	(
				in_mul55 => m1,
				out_mul55 => m1_55
				);

	m2_with_87: mul87
	port map	(
				in_mul87 => m2,
				out_mul87 => m2_87
				);

	m3_with_5a: mul5a
	port map	(
				in_mul5a => m3,
				out_mul5a => m3_5a
				);

	m4_with_58: mul58
	port map	(
				in_mul58 => m4,
				out_mul58 => m4_58
				);

	m5_with_db: muldb
	port map	(
				in_muldb => m5,
				out_muldb => m5_db
				);

	m6_with_9e: mul9e
	port map	(
				in_mul9e => m6,
				out_mul9e => m6_9e
				);

	m7_with_03: mul03
	port map	(
				in_mul03 => m7,
				out_mul03 => m7_03
				);


	-- we create the s1,j j=0..3
	-- the first row of m0..7 creates the s10
	m8_with_01: mul01
	port map	(
				in_mul01 => m8,
				out_mul01 => m8_01
				);

	m9_with_a4: mula4
	port map	(
				in_mula4 => m9,
				out_mula4 => m9_a4
				);

	m10_with_55: mul55
	port map	(
				in_mul55 => m10,
				out_mul55 => m10_55
				);

	m11_with_87: mul87
	port map	(
				in_mul87 => m11,
				out_mul87 => m11_87
				);

	m12_with_5a: mul5a
	port map	(
				in_mul5a => m12,
				out_mul5a => m12_5a
				);

	m13_with_58: mul58
	port map	(
				in_mul58 => m13,
				out_mul58 => m13_58
				);

	m14_with_db: muldb
	port map	(
				in_muldb => m14,
				out_muldb => m14_db
				);

	m15_with_9e: mul9e
	port map	(
				in_mul9e => m15,
				out_mul9e => m15_9e
				);

	-- the second row creates s11
	m8_with_a4: mula4
	port map	(
				in_mula4 => m8,
				out_mula4 => m8_a4
				);

	m9_with_56: mul56
	port map	(
				in_mul56 => m9,
				out_mul56 => m9_56
				);

	m10_with_82: mul82
	port map	(
				in_mul82 => m10,
				out_mul82 => m10_82
				);