stm32f10x_rcc.c

CAN 程序使用MCP2515 由STM32做主芯片控制

/*******************************************************************************
* File Name          : rcc.c
* Author             : 
* Date First Issued  : 03/31/2008
* Description        : Main program body
********************************************************************************/
/* -------------------------Includes ------------------------------------------------------------------*/
#include "..\header\stm32f10x_reg.h"
#include "..\header\type.h"
#include "..\header\mylib.h"
#include "..\header\rcc.h"
/*-----------------------------------------------------------------------*/
u32 rcc_intialize(void);
/*******************************************************************************
* Function Name  : rcc_deinit
* Description    : Resets the RCC clock configuration to the default reset state.
* Input          : None
* Output         : None
* Return         : None
*******************************************************************************/
void rcc_deinit(void)
{
  /* Set HSION bit */
  RCC->CR.W |= (u32)0x00000001;

  /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
  RCC->CFGR.W &= (u32)0xF8FF0000;
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR.W &= (u32)0xFEF6FFFF;

  /* Reset HSEBYP bit */
  RCC->CR.W &= (u32)0xFFFBFFFF;

  /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
  RCC->CFGR.W &= (u32)0xFF80FFFF;

  /* Disable all interrupts */
  RCC->CIR.W = 0x00000000;
}

/*******************************************************************************
* Function Name  : rcc_hseconfig
* Description    : Configures the External High Speed oscillator (HSE).
*                  HSE can not be stopped if it is used directly or through the 
*                  PLL as system clock.
* Input          : - RCC_HSE: specifies the new state of the HSE.
*                    This parameter can be one of the following values:
*                       - RCC_HSE=0: HSE oscillator OFF
*                       - RCC_HSE=1: HSE oscillator ON
*                       - RCC_HSE=2: HSE oscillator bypassed with external
*                         clock
* Output         : None
* Return         : None
*******************************************************************************/
void rcc_hseconfig(u32 RCC_HSE)
{
  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
  /* Reset HSEON bit */
  RCC->CR.W &= 0xFFFEFFFF;

  /* Reset HSEBYP bit */
  RCC->CR.W &= 0xFFFBFFFF;

  /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
  switch(RCC_HSE) {
	 case 1:
      /* Set HSEON bit */
      RCC->CR.B.HSEON=1;
      break;
      
    case 2:
      /* Set HSEBYP and HSEON bits */
      {
	  RCC->CR.B.HSEON=1;
	  RCC->CR.B.HSEBYP=1;
	  }
      break;            
    default:
      break;      
  }
  	 /* Wait till HSE is ready and if Time out is reached exit */
   // while(RCC->CR.B.HSERDY==0)	;
}

/*******************************************************************************
* Function Name  : rcc_hclkconfig
* Description    : Configures the AHB clock (HCLK).
* Input          : - RCC_SYSCLK: defines the AHB clock divider. This clock is
*                    derived from the system clock (SYSCLK).
*                    This parameter can be one of the following values:
*                       - RCC_SYSCLK_Div1: AHB clock = SYSCLK
*                       - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
*                       - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
*                       - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
*                       - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
*                       - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
*                       - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
*                       - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
*                       - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
* Output         : None
* Return         : None
*******************************************************************************/
void rcc_hclkconfig(u32 RCC_SYSCLK)
{
  /* Check the parameters */
  //assert_param(IS_RCC_HCLK(RCC_SYSCLK));

  /* Clear HPRE[3:0] bits */
  RCC->CFGR.B.HPRE=0;

  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
  RCC->CFGR.B.HPRE=RCC_SYSCLK;					   

}

/*******************************************************************************
* Function Name  : rcc_pclk1onfig
* Description    : Configures the Low Speed APB clock (PCLK1).
* Input          : - RCC_HCLK: defines the APB1 clock divider. This clock is
*                    derived from the AHB clock (HCLK).
*                    This parameter can be one of the following values:
*                       - RCC_HCLK_Div1: APB1 clock = HCLK
*                       - RCC_HCLK_Div2: APB1 clock = HCLK/2
*                       - RCC_HCLK_Div4: APB1 clock = HCLK/4
*                       - RCC_HCLK_Div8: APB1 clock = HCLK/8
*                       - RCC_HCLK_Div16: APB1 clock = HCLK/16
* Output         : None
* Return         : None
*******************************************************************************/
void rcc_pclk1Config(u32 RCC_HCLK)
{

  /* Check the parameters */
 // assert_param(IS_RCC_PCLK(RCC_HCLK));

  /* Clear PPRE1[2:0] bits */
  RCC->CFGR.B.PPRE1=0;

  /* Set PPRE1[2:0] bits according to RCC_HCLK value */
  RCC->CFGR.B.PPRE1=RCC_HCLK;

}

 /*******************************************************************************
* Function Name  : rcc_pclk2onfig
* Description    : Configures the High Speed APB clock (PCLK2).
* Input          : - RCC_HCLK: defines the APB2 clock divider. This clock is
*                    derived from the AHB clock (HCLK).
*                    This parameter can be one of the following values:
*                       - RCC_HCLK_Div1: APB2 clock = HCLK
*                       - RCC_HCLK_Div2: APB2 clock = HCLK/2
*                       - RCC_HCLK_Div4: APB2 clock = HCLK/4
*                       - RCC_HCLK_Div8: APB2 clock = HCLK/8
*                       - RCC_HCLK_Div16: APB2 clock = HCLK/16
* Output         : None
* Return         : None
*******************************************************************************/
void rcc_pclk2onfig(u32 RCC_HCLK)
{
  /* Check the parameters */
 // assert_param(IS_RCC_PCLK(RCC_HCLK));

  /* Clear PPRE2[2:0] bits */
  RCC->CFGR.B.PPRE2=0;

  /* Set PPRE2[2:0] bits according to RCC_HCLK value */
  RCC->CFGR.B.PPRE2= RCC_HCLK;
}

/*******************************************************************************
* Function Name  : rcc_pllconfig
* Description    : Configures the PLL clock source and multiplication factor.
*                  This function must be used only when the PLL is disabled.
* Input          : - RCC_PLLSource: specifies the PLL entry clock source.
*                    This parameter can be one of the following values:
*                       - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
*                         by 2 selected as PLL clock entry
*                       - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
*                         as PLL clock entry
*                       - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
*                         by 2 selected as PLL clock entry
*                  - RCC_PLLMul: specifies the PLL multiplication factor.
*                    This parameter can be RCC_PLLMul_x where x:[2,16]
* Output         : None
* Return         : None
*******************************************************************************/
void rcc_pllconfig(u32 RCC_PLLSource, u32 RCC_PLLMul)
{
  /* Check the parameters */
  //assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
 // assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));

  /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
  RCC->CFGR.B.PLLMUL=0;
  RCC->CFGR.B.PLLSRC=0;
  RCC->CFGR.B.PLLXTPRE=0;
  /* Set the PLL configuration bits */
  RCC->CFGR.B.PLLMUL=RCC_PLLMul;
  RCC->CFGR.B.SW=RCC_PLLSource;
// Enables or disables the PLL.
  RCC->CR.B.PLLON=1;
  while(RCC->CR.B.PLLRDY==1);
 }

 /*******************************************************************************
* Function Name  : rcc_sysclkconfig
* Description    : Configures the system clock (SYSCLK).
* Input          : - RCC_SYSCLKSource: specifies the clock source used as system
*                    clock. This parameter can be one of the following values:
*                       - RCC_SYSCLKSource_HSI: HSI selected as system clock
*                       - RCC_SYSCLKSource_HSE: HSE selected as system clock
*                       - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
* Output         : None
* Return         : None
*******************************************************************************/
void rcc_sysclkconfig(u32 RCC_SYSCLKSource)
{
  /* Check the parameters */
//  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));

  /* Clear SW[1:0] bits */
  RCC->CFGR.B.SW=0;

  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
  RCC->CFGR.B.SW=RCC_SYSCLKSource;
}
 /*******************************************************************************
* Function Name  : rcc_intialize
* Description    : 
* Input          : 
* Output         : None
* Return         : None
*******************************************************************************/
u32 rcc_intialize(void)
 {
	  rcc_deinit();
	  rcc_hseconfig(0);		//set the HSE clock;
	  rcc_hclkconfig(RCC_SYSCLK_Div1) ;		 //8*8*div1MHz;
	  rcc_pclk1Config(RCC_HCLK_Div2) ;		 //64/2
	  rcc_pclk2onfig(RCC_HCLK_Div2);	 	// 
	  rcc_pllconfig(RCC_PLLSource_HSE_Div2,RCC_PLLMul_8);	//PLL=8*8=64MHz
	  rcc_sysclkconfig(RCC_SYSCLKSource_PLLCLK);
	
	  
	   RCC->APB2ENR.W=0x00000000;
	   RCC->APB1ENR.W=0x00000000;
	   RCC->AHBENR.W=0x00000000;
	   RCC->APB2RSTR.B.SPI1RST=1;
	   RCC->APB2RSTR.B.SPI1RST=1;
	   RCC->APB2RSTR.B.SPI1RST=0;
	  // RCC->APB2ENR.B.SPI1EN=1;//enable the spi1 time	;
	   RCC->APB2ENR.B.IOPAEN =1;  //enable the GPIOa time  ;
	   RCC->APB2ENR.B.IOPBEN =1;  //enable the gpio_b time;  
	   RCC->APB2ENR.B.USART1EN =1;
//	 RCC->APB2ENR.B.AFIOEN=1;
	 //RCC->APB1ENR.B.SPI2EN=1;
     //RCC->APB1ENR.B.SPI3EN=1;
	// RCC->AHBENR.B.SDIOEN=1;  //enable the sdio funtion;
	

	return 0;
 }