statemachien.txt

基于状态图的光电编码器4倍频vhdl程序

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:55:13 04/13/2009 
-- Design Name: 
-- Module Name:    qep - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity qep is
port (clk,ina,inb,reset:in std_logic;
　dir,out1: out std_logic );
end qep;
architecture moore of qep is
type state_type is(s0,s1,s2,s3);
signal state1,state2:state_type;
signal temp_a,temp_b:std_logic;
begin
p1:process(clk)
begin
　if reset=’1’then
　　state1<=s0;
　elsif clk’event and clk=’1’then
　　case state1 is
　　　when s0=> if ina=’1’then
　　　　　state1 <= s1;
　　　　end if;
　　　when s1=> if ina=’1’then
　　　　　state1 <= s2;
　　　　end if;
　　　when s2=> if ina=’0’then
　　　　　state1 <= s3;
　　　　end if;
　　　when s3=> if ina=’0’then
　　　　　state1 <= s0;
　　　　end if;
　　end case;
　end if;
end process;
p2:process(clk)
begin
　if reset=’1’then
　　state2<=s0;
　elsif clk’event and clk=’1’then
　　case state2 is
　　　when s0=> if inb=’1’then
　　　　　state2 <= s1;
　　　　end if;
when s1=> if inb=’1’then
　　　　　state2 <= s2;
　　　　end if;
　　　when s2=> if inb=’0’then
　　　　　state2 <= s3;
　　　　end if;
　　　when s3=> if inb=’0’then
　　　　　state2 <= s0;
　　　　end if;
　　end case;
　end if;
end process;
outputa:process(state1)
begin
　case state1 is
　　when s0 => temp_a <=’0’;
　　when s1 => temp_a <=’1’;
　　when s2 => temp_a <=’0’;
　　when s3 => temp_a <=’1’;
　end case;
end process;
outputb:process(state2)
begin
　case state2 is
　　when s0 => temp_b <=’0’;
　　when s1 => temp_b <=’1’;
　　when s2 => temp_b <=’0’;
　　when s3 => temp_b <=’1’;
　end case;
end process;
out1 <= (temp_a or temp_b);
dir_process:process(ina)



begin
　if ina’event and ina=’1’then
　　dir<=inb;
　end if;
end process;
end moore;