div.tan.qmsg

用CPLD驱动数码管

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 2 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register divnum\[8\] register divnum\[18\] 115.37 MHz 8.668 ns Internal " "Info: Clock \"clk\" has Internal fmax of 115.37 MHz between source register \"divnum\[8\]\" and destination register \"divnum\[18\]\" (period= 8.668 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.959 ns + Longest register register " "Info: + Longest register to register delay is 7.959 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns divnum\[8\] 1 REG LC_X10_Y6_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y6_N7; Fanout = 4; REG Node = 'divnum\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { divnum[8] } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.030 ns) + CELL(0.978 ns) 3.008 ns Add0~403 2 COMB LC_X9_Y8_N1 2 " "Info: 2: + IC(2.030 ns) + CELL(0.978 ns) = 3.008 ns; Loc. = LC_X9_Y8_N1; Fanout = 2; COMB Node = 'Add0~403'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.008 ns" { divnum[8] Add0~403 } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 3.131 ns Add0~401 3 COMB LC_X9_Y8_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 3.131 ns; Loc. = LC_X9_Y8_N2; Fanout = 2; COMB Node = 'Add0~401'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.123 ns" { Add0~403 Add0~401 } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 3.254 ns Add0~399 4 COMB LC_X9_Y8_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 3.254 ns; Loc. = LC_X9_Y8_N3; Fanout = 2; COMB Node = 'Add0~399'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.123 ns" { Add0~401 Add0~399 } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 3.515 ns Add0~397 5 COMB LC_X9_Y8_N4 6 " "Info: 5: + IC(0.000 ns) + CELL(0.261 ns) = 3.515 ns; Loc. = LC_X9_Y8_N4; Fanout = 6; COMB Node = 'Add0~397'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.261 ns" { Add0~399 Add0~397 } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.349 ns) 3.864 ns Add0~385 6 COMB LC_X9_Y8_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.349 ns) = 3.864 ns; Loc. = LC_X9_Y8_N9; Fanout = 6; COMB Node = 'Add0~385'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.349 ns" { Add0~397 Add0~385 } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 5.098 ns Add0~382 7 COMB LC_X10_Y8_N1 1 " "Info: 7: + IC(0.000 ns) + CELL(1.234 ns) = 5.098 ns; Loc. = LC_X10_Y8_N1; Fanout = 1; COMB Node = 'Add0~382'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.234 ns" { Add0~385 Add0~382 } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.270 ns) + CELL(0.591 ns) 7.959 ns divnum\[18\] 8 REG LC_X12_Y8_N4 4 " "Info: 8: + IC(2.270 ns) + CELL(0.591 ns) = 7.959 ns; Loc. = LC_X12_Y8_N4; Fanout = 4; REG Node = 'divnum\[18\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.861 ns" { Add0~382 divnum[18] } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.659 ns ( 45.97 % ) " "Info: Total cell delay = 3.659 ns ( 45.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 54.03 % ) " "Info: Total interconnect delay = 4.300 ns ( 54.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.959 ns" { divnum[8] Add0~403 Add0~401 Add0~399 Add0~397 Add0~385 Add0~382 divnum[18] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.959 ns" { divnum[8] Add0~403 Add0~401 Add0~399 Add0~397 Add0~385 Add0~382 divnum[18] } { 0.000ns 2.030ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.270ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.261ns 0.349ns 1.234ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 42 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns divnum\[18\] 2 REG LC_X12_Y8_N4 4 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X12_Y8_N4; Fanout = 4; REG Node = 'divnum\[18\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.656 ns" { clk divnum[18] } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk divnum[18] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout divnum[18] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 42 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns divnum\[8\] 2 REG LC_X10_Y6_N7 4 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y6_N7; Fanout = 4; REG Node = 'divnum\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.656 ns" { clk divnum[8] } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk divnum[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout divnum[8] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk divnum[18] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout divnum[18] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk divnum[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout divnum[8] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.959 ns" { divnum[8] Add0~403 Add0~401 Add0~399 Add0~397 Add0~385 Add0~382 divnum[18] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.959 ns" { divnum[8] Add0~403 Add0~401 Add0~399 Add0~397 Add0~385 Add0~382 divnum[18] } { 0.000ns 2.030ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.270ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.261ns 0.349ns 1.234ns 0.591ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk divnum[18] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout divnum[18] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk divnum[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout divnum[8] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clkout clkout~reg0 8.560 ns register " "Info: tco from clock \"clk\" to destination pin \"clkout\" through register \"clkout~reg0\" is 8.560 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 42 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns clkout~reg0 2 REG LC_X12_Y8_N5 2 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X12_Y8_N5; Fanout = 2; REG Node = 'clkout~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.656 ns" { clk clkout~reg0 } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk clkout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout clkout~reg0 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.365 ns + Longest register pin " "Info: + Longest register to pin delay is 4.365 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clkout~reg0 1 REG LC_X12_Y8_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N5; Fanout = 2; REG Node = 'clkout~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkout~reg0 } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.043 ns) + CELL(2.322 ns) 4.365 ns clkout 2 PIN PIN_114 0 " "Info: 2: + IC(2.043 ns) + CELL(2.322 ns) = 4.365 ns; Loc. = PIN_114; Fanout = 0; PIN Node = 'clkout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.365 ns" { clkout~reg0 clkout } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 53.20 % ) " "Info: Total cell delay = 2.322 ns ( 53.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.043 ns ( 46.80 % ) " "Info: Total interconnect delay = 2.043 ns ( 46.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.365 ns" { clkout~reg0 clkout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.365 ns" { clkout~reg0 clkout } { 0.000ns 2.043ns } { 0.000ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk clkout~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout clkout~reg0 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.365 ns" { clkout~reg0 clkout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.365 ns" { clkout~reg0 clkout } { 0.000ns 2.043ns } { 0.000ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 25 16:03:04 2007 " "Info: Processing ended: Sat Aug 25 16:03:04 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}