jishuqi.tan.qmsg

用CPLD驱动数码管

{ "Info" "ITDB_TH_RESULT" "status4\[3\] rst clk1 -0.896 ns register " "Info: th for register \"status4\[3\]\" (data pin = \"rst\", clock pin = \"clk1\") is -0.896 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.990 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to destination register is 2.990 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk1 1 CLK PIN_M20 44 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 44; CLK Node = 'clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.620 ns) + CELL(0.542 ns) 2.990 ns status4\[3\] 2 REG LC_X35_Y11_N7 9 " "Info: 2: + IC(1.620 ns) + CELL(0.542 ns) = 2.990 ns; Loc. = LC_X35_Y11_N7; Fanout = 9; REG Node = 'status4\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.162 ns" { clk1 status4[3] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.82 % ) " "Info: Total cell delay = 1.370 ns ( 45.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.620 ns ( 54.18 % ) " "Info: Total interconnect delay = 1.620 ns ( 54.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.990 ns" { clk1 status4[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.990 ns" { clk1 clk1~out0 status4[3] } { 0.000ns 0.000ns 1.620ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.986 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns rst 1 PIN PIN_L20 48 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L20; Fanout = 48; PIN Node = 'rst'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.036 ns) + CELL(0.366 ns) 3.230 ns status2\[3\]~4 2 COMB LC_X35_Y11_N0 5 " "Info: 2: + IC(2.036 ns) + CELL(0.366 ns) = 3.230 ns; Loc. = LC_X35_Y11_N0; Fanout = 5; COMB Node = 'status2\[3\]~4'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.402 ns" { rst status2[3]~4 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.324 ns) + CELL(0.075 ns) 3.629 ns status4\[1\]~540 3 COMB LC_X35_Y11_N6 2 " "Info: 3: + IC(0.324 ns) + CELL(0.075 ns) = 3.629 ns; Loc. = LC_X35_Y11_N6; Fanout = 2; COMB Node = 'status4\[1\]~540'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.399 ns" { status2[3]~4 status4[1]~540 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.223 ns) 3.986 ns status4\[3\] 4 REG LC_X35_Y11_N7 9 " "Info: 4: + IC(0.134 ns) + CELL(0.223 ns) = 3.986 ns; Loc. = LC_X35_Y11_N7; Fanout = 9; REG Node = 'status4\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.357 ns" { status4[1]~540 status4[3] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.492 ns ( 37.43 % ) " "Info: Total cell delay = 1.492 ns ( 37.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.494 ns ( 62.57 % ) " "Info: Total interconnect delay = 2.494 ns ( 62.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.986 ns" { rst status2[3]~4 status4[1]~540 status4[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.986 ns" { rst rst~out0 status2[3]~4 status4[1]~540 status4[3] } { 0.000ns 0.000ns 2.036ns 0.324ns 0.134ns } { 0.000ns 0.828ns 0.366ns 0.075ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.990 ns" { clk1 status4[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.990 ns" { clk1 clk1~out0 status4[3] } { 0.000ns 0.000ns 1.620ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.986 ns" { rst status2[3]~4 status4[1]~540 status4[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.986 ns" { rst rst~out0 status2[3]~4 status4[1]~540 status4[3] } { 0.000ns 0.000ns 2.036ns 0.324ns 0.134ns } { 0.000ns 0.828ns 0.366ns 0.075ns 0.223ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 25 16:00:00 2007 " "Info: Processing ended: Sat Aug 25 16:00:00 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}