jishuqi.tan.qmsg

用CPLD驱动数码管

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register com.0001 register seg1\[5\]~reg0 372.58 MHz 2.684 ns Internal " "Info: Clock \"clk\" has Internal fmax of 372.58 MHz between source register \"com.0001\" and destination register \"seg1\[5\]~reg0\" (period= 2.684 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.533 ns + Longest register register " "Info: + Longest register to register delay is 2.533 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns com.0001 1 REG LC_X35_Y8_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y8_N5; Fanout = 4; REG Node = 'com.0001'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { com.0001 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.183 ns) 0.611 ns seg1\[0\]~369 2 COMB LC_X35_Y8_N9 11 " "Info: 2: + IC(0.428 ns) + CELL(0.183 ns) = 0.611 ns; Loc. = LC_X35_Y8_N9; Fanout = 11; COMB Node = 'seg1\[0\]~369'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.611 ns" { com.0001 seg1[0]~369 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.183 ns) 1.334 ns seg1~382 3 COMB LC_X36_Y8_N7 1 " "Info: 3: + IC(0.540 ns) + CELL(0.183 ns) = 1.334 ns; Loc. = LC_X36_Y8_N7; Fanout = 1; COMB Node = 'seg1~382'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.723 ns" { seg1[0]~369 seg1~382 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.976 ns) + CELL(0.223 ns) 2.533 ns seg1\[5\]~reg0 4 REG LC_X36_Y9_N4 1 " "Info: 4: + IC(0.976 ns) + CELL(0.223 ns) = 2.533 ns; Loc. = LC_X36_Y9_N4; Fanout = 1; REG Node = 'seg1\[5\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.199 ns" { seg1~382 seg1[5]~reg0 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.589 ns ( 23.25 % ) " "Info: Total cell delay = 0.589 ns ( 23.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.944 ns ( 76.75 % ) " "Info: Total interconnect delay = 1.944 ns ( 76.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.533 ns" { com.0001 seg1[0]~369 seg1~382 seg1[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.533 ns" { com.0001 seg1[0]~369 seg1~382 seg1[5]~reg0 } { 0.000ns 0.428ns 0.540ns 0.976ns } { 0.000ns 0.183ns 0.183ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.015 ns - Smallest " "Info: - Smallest clock skew is 0.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.894 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.894 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_M21 14 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.627 ns) + CELL(0.542 ns) 2.894 ns seg1\[5\]~reg0 2 REG LC_X36_Y9_N4 1 " "Info: 2: + IC(1.627 ns) + CELL(0.542 ns) = 2.894 ns; Loc. = LC_X36_Y9_N4; Fanout = 1; REG Node = 'seg1\[5\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.169 ns" { clk seg1[5]~reg0 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 43.78 % ) " "Info: Total cell delay = 1.267 ns ( 43.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.627 ns ( 56.22 % ) " "Info: Total interconnect delay = 1.627 ns ( 56.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.894 ns" { clk seg1[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.894 ns" { clk clk~out0 seg1[5]~reg0 } { 0.000ns 0.000ns 1.627ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.879 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.879 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_M21 14 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.612 ns) + CELL(0.542 ns) 2.879 ns com.0001 2 REG LC_X35_Y8_N5 4 " "Info: 2: + IC(1.612 ns) + CELL(0.542 ns) = 2.879 ns; Loc. = LC_X35_Y8_N5; Fanout = 4; REG Node = 'com.0001'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.154 ns" { clk com.0001 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.01 % ) " "Info: Total cell delay = 1.267 ns ( 44.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.612 ns ( 55.99 % ) " "Info: Total interconnect delay = 1.612 ns ( 55.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.879 ns" { clk com.0001 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.879 ns" { clk clk~out0 com.0001 } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.894 ns" { clk seg1[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.894 ns" { clk clk~out0 seg1[5]~reg0 } { 0.000ns 0.000ns 1.627ns } { 0.000ns 0.725ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.879 ns" { clk com.0001 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.879 ns" { clk clk~out0 com.0001 } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 183 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.533 ns" { com.0001 seg1[0]~369 seg1~382 seg1[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.533 ns" { com.0001 seg1[0]~369 seg1~382 seg1[5]~reg0 } { 0.000ns 0.428ns 0.540ns 0.976ns } { 0.000ns 0.183ns 0.183ns 0.223ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.894 ns" { clk seg1[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.894 ns" { clk clk~out0 seg1[5]~reg0 } { 0.000ns 0.000ns 1.627ns } { 0.000ns 0.725ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.879 ns" { clk com.0001 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.879 ns" { clk clk~out0 com.0001 } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register status\[0\] register status2\[0\] 332.56 MHz 3.007 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 332.56 MHz between source register \"status\[0\]\" and destination register \"status2\[0\]\" (period= 3.007 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.864 ns + Longest register register " "Info: + Longest register to register delay is 2.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns status\[0\] 1 REG LC_X36_Y9_N2 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y9_N2; Fanout = 12; REG Node = 'status\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { status[0] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.075 ns) 1.118 ns Equal0~91 2 COMB LC_X35_Y11_N3 2 " "Info: 2: + IC(1.043 ns) + CELL(0.075 ns) = 1.118 ns; Loc. = LC_X35_Y11_N3; Fanout = 2; COMB Node = 'Equal0~91'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.118 ns" { status[0] Equal0~91 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.327 ns) + CELL(0.183 ns) 1.628 ns status2\[3\]~4 3 COMB LC_X35_Y11_N0 5 " "Info: 3: + IC(0.327 ns) + CELL(0.183 ns) = 1.628 ns; Loc. = LC_X35_Y11_N0; Fanout = 5; COMB Node = 'status2\[3\]~4'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.510 ns" { Equal0~91 status2[3]~4 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.531 ns) + CELL(0.705 ns) 2.864 ns status2\[0\] 4 REG LC_X36_Y11_N1 12 " "Info: 4: + IC(0.531 ns) + CELL(0.705 ns) = 2.864 ns; Loc. = LC_X36_Y11_N1; Fanout = 12; REG Node = 'status2\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.236 ns" { status2[3]~4 status2[0] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.963 ns ( 33.62 % ) " "Info: Total cell delay = 0.963 ns ( 33.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.901 ns ( 66.38 % ) " "Info: Total interconnect delay = 1.901 ns ( 66.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.864 ns" { status[0] Equal0~91 status2[3]~4 status2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.864 ns" { status[0] Equal0~91 status2[3]~4 status2[0] } { 0.000ns 1.043ns 0.327ns 0.531ns } { 0.000ns 0.075ns 0.183ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.023 ns - Smallest " "Info: - Smallest clock skew is 0.023 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.990 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 2.990 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk1 1 CLK PIN_M20 44 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 44; CLK Node = 'clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.620 ns) + CELL(0.542 ns) 2.990 ns status2\[0\] 2 REG LC_X36_Y11_N1 12 " "Info: 2: + IC(1.620 ns) + CELL(0.542 ns) = 2.990 ns; Loc. = LC_X36_Y11_N1; Fanout = 12; REG Node = 'status2\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.162 ns" { clk1 status2[0] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.82 % ) " "Info: Total cell delay = 1.370 ns ( 45.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.620 ns ( 54.18 % ) " "Info: Total interconnect delay = 1.620 ns ( 54.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.990 ns" { clk1 status2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.990 ns" { clk1 clk1~out0 status2[0] } { 0.000ns 0.000ns 1.620ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.967 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 2.967 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk1 1 CLK PIN_M20 44 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 44; CLK Node = 'clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.597 ns) + CELL(0.542 ns) 2.967 ns status\[0\] 2 REG LC_X36_Y9_N2 12 " "Info: 2: + IC(1.597 ns) + CELL(0.542 ns) = 2.967 ns; Loc. = LC_X36_Y9_N2; Fanout = 12; REG Node = 'status\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk1 status[0] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.17 % ) " "Info: Total cell delay = 1.370 ns ( 46.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.597 ns ( 53.83 % ) " "Info: Total interconnect delay = 1.597 ns ( 53.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.967 ns" { clk1 status[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.967 ns" { clk1 clk1~out0 status[0] } { 0.000ns 0.000ns 1.597ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.990 ns" { clk1 status2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.990 ns" { clk1 clk1~out0 status2[0] } { 0.000ns 0.000ns 1.620ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.967 ns" { clk1 status[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.967 ns" { clk1 clk1~out0 status[0] } { 0.000ns 0.000ns 1.597ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.864 ns" { status[0] Equal0~91 status2[3]~4 status2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.864 ns" { status[0] Equal0~91 status2[3]~4 status2[0] } { 0.000ns 1.043ns 0.327ns 0.531ns } { 0.000ns 0.075ns 0.183ns 0.705ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.990 ns" { clk1 status2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.990 ns" { clk1 clk1~out0 status2[0] } { 0.000ns 0.000ns 1.620ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.967 ns" { clk1 status[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.967 ns" { clk1 clk1~out0 status[0] } { 0.000ns 0.000ns 1.597ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "status4\[0\] rst clk1 1.489 ns register " "Info: tsu for register \"status4\[0\]\" (data pin = \"rst\", clock pin = \"clk1\") is 1.489 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.457 ns + Longest pin register " "Info: + Longest pin to register delay is 4.457 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns rst 1 PIN PIN_L20 48 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L20; Fanout = 48; PIN Node = 'rst'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.034 ns) + CELL(0.366 ns) 3.228 ns status3\[0\]~294 2 COMB LC_X35_Y11_N4 6 " "Info: 2: + IC(2.034 ns) + CELL(0.366 ns) = 3.228 ns; Loc. = LC_X35_Y11_N4; Fanout = 6; COMB Node = 'status3\[0\]~294'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { rst status3[0]~294 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.223 ns) 4.457 ns status4\[0\] 3 REG LC_X35_Y10_N4 10 " "Info: 3: + IC(1.006 ns) + CELL(0.223 ns) = 4.457 ns; Loc. = LC_X35_Y10_N4; Fanout = 10; REG Node = 'status4\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.229 ns" { status3[0]~294 status4[0] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.417 ns ( 31.79 % ) " "Info: Total cell delay = 1.417 ns ( 31.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.040 ns ( 68.21 % ) " "Info: Total interconnect delay = 3.040 ns ( 68.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.457 ns" { rst status3[0]~294 status4[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.457 ns" { rst rst~out0 status3[0]~294 status4[0] } { 0.000ns 0.000ns 2.034ns 1.006ns } { 0.000ns 0.828ns 0.366ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.978 ns - Shortest register " "Info: - Shortest clock path from clock \"clk1\" to destination register is 2.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk1 1 CLK PIN_M20 44 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 44; CLK Node = 'clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.608 ns) + CELL(0.542 ns) 2.978 ns status4\[0\] 2 REG LC_X35_Y10_N4 10 " "Info: 2: + IC(1.608 ns) + CELL(0.542 ns) = 2.978 ns; Loc. = LC_X35_Y10_N4; Fanout = 10; REG Node = 'status4\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.150 ns" { clk1 status4[0] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.00 % ) " "Info: Total cell delay = 1.370 ns ( 46.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.608 ns ( 54.00 % ) " "Info: Total interconnect delay = 1.608 ns ( 54.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.978 ns" { clk1 status4[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.978 ns" { clk1 clk1~out0 status4[0] } { 0.000ns 0.000ns 1.608ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.457 ns" { rst status3[0]~294 status4[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.457 ns" { rst rst~out0 status3[0]~294 status4[0] } { 0.000ns 0.000ns 2.034ns 1.006ns } { 0.000ns 0.828ns 0.366ns 0.223ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.978 ns" { clk1 status4[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.978 ns" { clk1 clk1~out0 status4[0] } { 0.000ns 0.000ns 1.608ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk com1\[0\] com.0001 7.340 ns register " "Info: tco from clock \"clk\" to destination pin \"com1\[0\]\" through register \"com.0001\" is 7.340 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.879 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.879 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_M21 14 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 14; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.612 ns) + CELL(0.542 ns) 2.879 ns com.0001 2 REG LC_X35_Y8_N5 4 " "Info: 2: + IC(1.612 ns) + CELL(0.542 ns) = 2.879 ns; Loc. = LC_X35_Y8_N5; Fanout = 4; REG Node = 'com.0001'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.154 ns" { clk com.0001 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.01 % ) " "Info: Total cell delay = 1.267 ns ( 44.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.612 ns ( 55.99 % ) " "Info: Total interconnect delay = 1.612 ns ( 55.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.879 ns" { clk com.0001 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.879 ns" { clk clk~out0 com.0001 } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.305 ns + Longest register pin " "Info: + Longest register to pin delay is 4.305 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns com.0001 1 REG LC_X35_Y8_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y8_N5; Fanout = 4; REG Node = 'com.0001'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { com.0001 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.901 ns) + CELL(2.404 ns) 4.305 ns com1\[0\] 2 PIN PIN_P10 0 " "Info: 2: + IC(1.901 ns) + CELL(2.404 ns) = 4.305 ns; Loc. = PIN_P10; Fanout = 0; PIN Node = 'com1\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.305 ns" { com.0001 com1[0] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 55.84 % ) " "Info: Total cell delay = 2.404 ns ( 55.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.901 ns ( 44.16 % ) " "Info: Total interconnect delay = 1.901 ns ( 44.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.305 ns" { com.0001 com1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.305 ns" { com.0001 com1[0] } { 0.000ns 1.901ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.879 ns" { clk com.0001 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.879 ns" { clk clk~out0 com.0001 } { 0.000ns 0.000ns 1.612ns } { 0.000ns 0.725ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.305 ns" { com.0001 com1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.305 ns" { com.0001 com1[0] } { 0.000ns 1.901ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}