hao.map.qmsg

用CPLD驱动数码管

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 jishuqi.v(208) " "Warning (10230): Verilog HDL assignment warning at jishuqi.v(208): truncated value with size 5 to match size of target (4)" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 208 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "div.v(10) " "Warning (10268): Verilog HDL information at div.v(10): Always Construct contains both blocking and non-blocking assignments" {  } { { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 10 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "div.v(23) " "Warning (10268): Verilog HDL information at div.v(23): Always Construct contains both blocking and non-blocking assignments" {  } { { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 23 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Warning" "WSGN_SEARCH_FILE" "div.v 1 1 " "Warning: Using design file div.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 div " "Info: Found entity 1: div" {  } { { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div div:inst " "Info: Elaborating entity \"div\" for hierarchy \"div:inst\"" {  } { { "hao.bdf" "inst" { Schematic "E:/VERIL/shumaguan/hao.bdf" { { 16 120 216 112 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 25 div.v(19) " "Warning (10230): Verilog HDL assignment warning at div.v(19): truncated value with size 32 to match size of target (25)" {  } { { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 15 div.v(32) " "Warning (10230): Verilog HDL assignment warning at div.v(32): truncated value with size 32 to match size of target (15)" {  } { { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|hao\|jishuqi:inst1\|com 5 " "Info: State machine \"\|hao\|jishuqi:inst1\|com\" contains 5 states" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|hao\|jishuqi:inst1\|com " "Info: Selected Auto state machine encoding method for state machine \"\|hao\|jishuqi:inst1\|com\"" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|hao\|jishuqi:inst1\|com " "Info: Encoding result for state machine \"\|hao\|jishuqi:inst1\|com\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jishuqi:inst1\|com.0000 " "Info: Encoded state bit \"jishuqi:inst1\|com.0000\"" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jishuqi:inst1\|com.1000 " "Info: Encoded state bit \"jishuqi:inst1\|com.1000\"" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jishuqi:inst1\|com.0100 " "Info: Encoded state bit \"jishuqi:inst1\|com.0100\"" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jishuqi:inst1\|com.0010 " "Info: Encoded state bit \"jishuqi:inst1\|com.0010\"" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jishuqi:inst1\|com.0001 " "Info: Encoded state bit \"jishuqi:inst1\|com.0001\"" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|hao\|jishuqi:inst1\|com.0000 00000 " "Info: State \"\|hao\|jishuqi:inst1\|com.0000\" uses code string \"00000\"" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|hao\|jishuqi:inst1\|com.0100 10100 " "Info: State \"\|hao\|jishuqi:inst1\|com.0100\" uses code string \"10100\"" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|hao\|jishuqi:inst1\|com.0010 10010 " "Info: State \"\|hao\|jishuqi:inst1\|com.0010\" uses code string \"10010\"" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|hao\|jishuqi:inst1\|com.0001 10001 " "Info: State \"\|hao\|jishuqi:inst1\|com.0001\" uses code string \"10001\"" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|hao\|jishuqi:inst1\|com.1000 11000 " "Info: State \"\|hao\|jishuqi:inst1\|com.1000\" uses code string \"11000\"" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 7 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 183 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 183 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 183 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 183 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 183 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 183 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 183 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 135 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 159 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 87 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 111 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 159 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 135 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 87 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 111 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 135 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 159 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 87 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 111 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 159 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 135 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 87 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 111 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 135 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 159 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 87 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 111 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 159 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 135 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 87 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 111 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 135 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 159 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 87 -1 0 } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 111 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "181 " "Info: Implemented 181 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "168 " "Info: Implemented 168 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 04 14:14:20 2007 " "Info: Processing ended: Sun Nov 04 14:14:20 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/VERIL/shumaguan/hao.map.smsg " "Info: Generated suppressed messages file E:/VERIL/shumaguan/hao.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}