div.tan.rpt

用CPLD驱动数码管

; N/A                                     ; 137.59 MHz ( period = 7.268 ns )                    ; divnum[13] ; divnum[0]   ; clk        ; clk      ; None                        ; None                      ; 6.559 ns                ;
; N/A                                     ; 137.63 MHz ( period = 7.266 ns )                    ; divnum[16] ; divnum[17]  ; clk        ; clk      ; None                        ; None                      ; 6.557 ns                ;
; N/A                                     ; 137.65 MHz ( period = 7.265 ns )                    ; divnum[5]  ; divnum[9]   ; clk        ; clk      ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 137.65 MHz ( period = 7.265 ns )                    ; divnum[6]  ; divnum[8]   ; clk        ; clk      ; None                        ; None                      ; 6.556 ns                ;
; N/A                                     ; 137.91 MHz ( period = 7.251 ns )                    ; divnum[9]  ; divnum[21]  ; clk        ; clk      ; None                        ; None                      ; 6.542 ns                ;
; N/A                                     ; 138.06 MHz ( period = 7.243 ns )                    ; divnum[7]  ; divnum[10]  ; clk        ; clk      ; None                        ; None                      ; 6.534 ns                ;
; N/A                                     ; 138.12 MHz ( period = 7.240 ns )                    ; divnum1[3] ; divnum1[0]  ; clk        ; clk      ; None                        ; None                      ; 6.531 ns                ;
; N/A                                     ; 138.14 MHz ( period = 7.239 ns )                    ; divnum1[5] ; divnum1[0]  ; clk        ; clk      ; None                        ; None                      ; 6.530 ns                ;
; N/A                                     ; 138.18 MHz ( period = 7.237 ns )                    ; divnum[3]  ; divnum[19]  ; clk        ; clk      ; None                        ; None                      ; 6.528 ns                ;
; N/A                                     ; 138.26 MHz ( period = 7.233 ns )                    ; divnum[22] ; divnum[24]  ; clk        ; clk      ; None                        ; None                      ; 6.524 ns                ;
; N/A                                     ; 138.29 MHz ( period = 7.231 ns )                    ; divnum[9]  ; divnum[16]  ; clk        ; clk      ; None                        ; None                      ; 6.522 ns                ;
; N/A                                     ; 138.31 MHz ( period = 7.230 ns )                    ; divnum[11] ; divnum[13]  ; clk        ; clk      ; None                        ; None                      ; 6.521 ns                ;
; N/A                                     ; 138.56 MHz ( period = 7.217 ns )                    ; divnum[5]  ; divnum[7]   ; clk        ; clk      ; None                        ; None                      ; 6.508 ns                ;
; N/A                                     ; 138.60 MHz ( period = 7.215 ns )                    ; divnum[6]  ; divnum[9]   ; clk        ; clk      ; None                        ; None                      ; 6.506 ns                ;
; N/A                                     ; 138.81 MHz ( period = 7.204 ns )                    ; divnum[8]  ; divnum[15]  ; clk        ; clk      ; None                        ; None                      ; 6.495 ns                ;
; N/A                                     ; 138.85 MHz ( period = 7.202 ns )                    ; divnum1[4] ; divnum1[12] ; clk        ; clk      ; None                        ; None                      ; 6.493 ns                ;
; N/A                                     ; 138.91 MHz ( period = 7.199 ns )                    ; divnum[0]  ; divnum[19]  ; clk        ; clk      ; None                        ; None                      ; 6.490 ns                ;
; N/A                                     ; 138.97 MHz ( period = 7.196 ns )                    ; divnum[10] ; divnum[12]  ; clk        ; clk      ; None                        ; None                      ; 6.487 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;             ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To     ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A   ; None         ; 8.560 ns   ; clkout~reg0 ; clkout ; clk        ;
; N/A   ; None         ; 8.458 ns   ; clkg~reg0   ; clkg   ; clk        ;
+-------+--------------+------------+-------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Aug 25 16:03:02 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div -c div
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 115.37 MHz between source register "divnum[8]" and destination register "divnum[18]" (period= 8.668 ns)
    Info: + Longest register to register delay is 7.959 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y6_N7; Fanout = 4; REG Node = 'divnum[8]'
        Info: 2: + IC(2.030 ns) + CELL(0.978 ns) = 3.008 ns; Loc. = LC_X9_Y8_N1; Fanout = 2; COMB Node = 'Add0~403'
        Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 3.131 ns; Loc. = LC_X9_Y8_N2; Fanout = 2; COMB Node = 'Add0~401'
        Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 3.254 ns; Loc. = LC_X9_Y8_N3; Fanout = 2; COMB Node = 'Add0~399'
        Info: 5: + IC(0.000 ns) + CELL(0.261 ns) = 3.515 ns; Loc. = LC_X9_Y8_N4; Fanout = 6; COMB Node = 'Add0~397'
        Info: 6: + IC(0.000 ns) + CELL(0.349 ns) = 3.864 ns; Loc. = LC_X9_Y8_N9; Fanout = 6; COMB Node = 'Add0~385'
        Info: 7: + IC(0.000 ns) + CELL(1.234 ns) = 5.098 ns; Loc. = LC_X10_Y8_N1; Fanout = 1; COMB Node = 'Add0~382'
        Info: 8: + IC(2.270 ns) + CELL(0.591 ns) = 7.959 ns; Loc. = LC_X12_Y8_N4; Fanout = 4; REG Node = 'divnum[18]'
        Info: Total cell delay = 3.659 ns ( 45.97 % )
        Info: Total interconnect delay = 4.300 ns ( 54.03 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.819 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X12_Y8_N4; Fanout = 4; REG Node = 'divnum[18]'
            Info: Total cell delay = 2.081 ns ( 54.49 % )
            Info: Total interconnect delay = 1.738 ns ( 45.51 % )
        Info: - Longest clock path from clock "clk" to source register is 3.819 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y6_N7; Fanout = 4; REG Node = 'divnum[8]'
            Info: Total cell delay = 2.081 ns ( 54.49 % )
            Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "clkout" through register "clkout~reg0" is 8.560 ns
    Info: + Longest clock path from clock "clk" to source register is 3.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X12_Y8_N5; Fanout = 2; REG Node = 'clkout~reg0'
        Info: Total cell delay = 2.081 ns ( 54.49 % )
        Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.365 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N5; Fanout = 2; REG Node = 'clkout~reg0'
        Info: 2: + IC(2.043 ns) + CELL(2.322 ns) = 4.365 ns; Loc. = PIN_114; Fanout = 0; PIN Node = 'clkout'
        Info: Total cell delay = 2.322 ns ( 53.20 % )
        Info: Total interconnect delay = 2.043 ns ( 46.80 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Aug 25 16:03:04 2007
    Info: Elapsed time: 00:00:03