hao.map.qmsg

用CPLD驱动数码管

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 25 16:52:43 2007 " "Info: Processing started: Sat Aug 25 16:52:43 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off hao -c hao " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hao -c hao" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hao.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file hao.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 hao " "Info: Found entity 1: hao" {  } { { "hao.bdf" "" { Schematic "E:/VERIL/shumaguan/hao.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "hao " "Info: Elaborating entity \"hao\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "jishuqi.v(85) " "Warning (10268): Verilog HDL information at jishuqi.v(85): Always Construct contains both blocking and non-blocking assignments" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 85 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "jishuqi.v(109) " "Warning (10268): Verilog HDL information at jishuqi.v(109): Always Construct contains both blocking and non-blocking assignments" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 109 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "jishuqi.v(133) " "Warning (10268): Verilog HDL information at jishuqi.v(133): Always Construct contains both blocking and non-blocking assignments" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 133 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "jishuqi.v(157) " "Warning (10268): Verilog HDL information at jishuqi.v(157): Always Construct contains both blocking and non-blocking assignments" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 157 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Warning" "WSGN_SEARCH_FILE" "jishuqi.v 1 1 " "Warning: Using design file jishuqi.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 jishuqi " "Info: Found entity 1: jishuqi" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jishuqi jishuqi:inst1 " "Info: Elaborating entity \"jishuqi\" for hierarchy \"jishuqi:inst1\"" {  } { { "hao.bdf" "inst1" { Schematic "E:/VERIL/shumaguan/hao.bdf" { { 16 280 408 112 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 jishuqi.v(20) " "Warning (10230): Verilog HDL assignment warning at jishuqi.v(20): truncated value with size 32 to match size of target (2)" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jishuqi.v(65) " "Warning (10230): Verilog HDL assignment warning at jishuqi.v(65): truncated value with size 32 to match size of target (4)" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jishuqi.v(70) " "Warning (10230): Verilog HDL assignment warning at jishuqi.v(70): truncated value with size 32 to match size of target (4)" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jishuqi.v(75) " "Warning (10230): Verilog HDL assignment warning at jishuqi.v(75): truncated value with size 32 to match size of target (4)" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 75 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jishuqi.v(80) " "Warning (10230): Verilog HDL assignment warning at jishuqi.v(80): truncated value with size 32 to match size of target (4)" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 80 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}