hao.tan.qmsg

用CPLD驱动数码管

{ "Info" "ITDB_TH_RESULT" "jishuqi:inst1\|status2\[2\] reset clk 1.430 ns register " "Info: th for register \"jishuqi:inst1\|status2\[2\]\" (data pin = \"reset\", clock pin = \"clk\") is 1.430 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.677 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 42 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "hao.bdf" "" { Schematic "E:/VERIL/shumaguan/hao.bdf" { { 40 -88 80 56 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns div:inst\|clkout 2 REG LC_X14_Y3_N4 45 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X14_Y3_N4; Fanout = 45; REG Node = 'div:inst\|clkout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.032 ns" { clk div:inst|clkout } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.564 ns) + CELL(0.918 ns) 8.677 ns jishuqi:inst1\|status2\[2\] 3 REG LC_X14_Y7_N4 11 " "Info: 3: + IC(3.564 ns) + CELL(0.918 ns) = 8.677 ns; Loc. = LC_X14_Y7_N4; Fanout = 11; REG Node = 'jishuqi:inst1\|status2\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.482 ns" { div:inst|clkout jishuqi:inst1|status2[2] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 38.90 % ) " "Info: Total cell delay = 3.375 ns ( 38.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.302 ns ( 61.10 % ) " "Info: Total interconnect delay = 5.302 ns ( 61.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.677 ns" { clk div:inst|clkout jishuqi:inst1|status2[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.677 ns" { clk clk~combout div:inst|clkout jishuqi:inst1|status2[2] } { 0.000ns 0.000ns 1.738ns 3.564ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.468 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_93 49 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_93; Fanout = 49; PIN Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "hao.bdf" "" { Schematic "E:/VERIL/shumaguan/hao.bdf" { { 168 -24 144 184 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.485 ns) + CELL(0.200 ns) 5.817 ns jishuqi:inst1\|status2\[3\]~4 2 COMB LC_X14_Y7_N6 4 " "Info: 2: + IC(4.485 ns) + CELL(0.200 ns) = 5.817 ns; Loc. = LC_X14_Y7_N6; Fanout = 4; COMB Node = 'jishuqi:inst1\|status2\[3\]~4'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.685 ns" { reset jishuqi:inst1|status2[3]~4 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.847 ns) + CELL(0.804 ns) 7.468 ns jishuqi:inst1\|status2\[2\] 3 REG LC_X14_Y7_N4 11 " "Info: 3: + IC(0.847 ns) + CELL(0.804 ns) = 7.468 ns; Loc. = LC_X14_Y7_N4; Fanout = 11; REG Node = 'jishuqi:inst1\|status2\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.651 ns" { jishuqi:inst1|status2[3]~4 jishuqi:inst1|status2[2] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.136 ns ( 28.60 % ) " "Info: Total cell delay = 2.136 ns ( 28.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.332 ns ( 71.40 % ) " "Info: Total interconnect delay = 5.332 ns ( 71.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.468 ns" { reset jishuqi:inst1|status2[3]~4 jishuqi:inst1|status2[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.468 ns" { reset reset~combout jishuqi:inst1|status2[3]~4 jishuqi:inst1|status2[2] } { 0.000ns 0.000ns 4.485ns 0.847ns } { 0.000ns 1.132ns 0.200ns 0.804ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.677 ns" { clk div:inst|clkout jishuqi:inst1|status2[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.677 ns" { clk clk~combout div:inst|clkout jishuqi:inst1|status2[2] } { 0.000ns 0.000ns 1.738ns 3.564ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.468 ns" { reset jishuqi:inst1|status2[3]~4 jishuqi:inst1|status2[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.468 ns" { reset reset~combout jishuqi:inst1|status2[3]~4 jishuqi:inst1|status2[2] } { 0.000ns 0.000ns 4.485ns 0.847ns } { 0.000ns 1.132ns 0.200ns 0.804ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 25 16:53:05 2007 " "Info: Processing ended: Sat Aug 25 16:53:05 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}