hao.tan.qmsg

用CPLD驱动数码管

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "hao.bdf" "" { Schematic "E:/VERIL/shumaguan/hao.bdf" { { 40 -88 80 56 "clk" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div:inst\|clkout " "Info: Detected ripple clock \"div:inst\|clkout\" as buffer" {  } { { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 3 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "div:inst\|clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div:inst\|clkg " "Info: Detected ripple clock \"div:inst\|clkg\" as buffer" {  } { { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 3 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "div:inst\|clkg" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register div:inst\|divnum\[8\] register div:inst\|divnum\[0\] 110.61 MHz 9.041 ns Internal " "Info: Clock \"clk\" has Internal fmax of 110.61 MHz between source register \"div:inst\|divnum\[8\]\" and destination register \"div:inst\|divnum\[0\]\" (period= 9.041 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.332 ns + Longest register register " "Info: + Longest register to register delay is 8.332 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div:inst\|divnum\[8\] 1 REG LC_X16_Y2_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y2_N2; Fanout = 4; REG Node = 'div:inst\|divnum\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { div:inst|divnum[8] } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.159 ns) + CELL(0.740 ns) 2.899 ns div:inst\|Equal0~274 2 COMB LC_X15_Y3_N6 1 " "Info: 2: + IC(2.159 ns) + CELL(0.740 ns) = 2.899 ns; Loc. = LC_X15_Y3_N6; Fanout = 1; COMB Node = 'div:inst\|Equal0~274'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.899 ns" { div:inst|divnum[8] div:inst|Equal0~274 } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.733 ns) + CELL(0.914 ns) 4.546 ns div:inst\|Equal0~275 3 COMB LC_X15_Y3_N4 1 " "Info: 3: + IC(0.733 ns) + CELL(0.914 ns) = 4.546 ns; Loc. = LC_X15_Y3_N4; Fanout = 1; COMB Node = 'div:inst\|Equal0~275'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.647 ns" { div:inst|Equal0~274 div:inst|Equal0~275 } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.200 ns) 5.280 ns div:inst\|Equal0~278 4 COMB LC_X15_Y3_N5 14 " "Info: 4: + IC(0.534 ns) + CELL(0.200 ns) = 5.280 ns; Loc. = LC_X15_Y3_N5; Fanout = 14; COMB Node = 'div:inst\|Equal0~278'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.734 ns" { div:inst|Equal0~275 div:inst|Equal0~278 } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.461 ns) + CELL(0.591 ns) 8.332 ns div:inst\|divnum\[0\] 5 REG LC_X13_Y2_N2 4 " "Info: 5: + IC(2.461 ns) + CELL(0.591 ns) = 8.332 ns; Loc. = LC_X13_Y2_N2; Fanout = 4; REG Node = 'div:inst\|divnum\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.052 ns" { div:inst|Equal0~278 div:inst|divnum[0] } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.445 ns ( 29.34 % ) " "Info: Total cell delay = 2.445 ns ( 29.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.887 ns ( 70.66 % ) " "Info: Total interconnect delay = 5.887 ns ( 70.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.332 ns" { div:inst|divnum[8] div:inst|Equal0~274 div:inst|Equal0~275 div:inst|Equal0~278 div:inst|divnum[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.332 ns" { div:inst|divnum[8] div:inst|Equal0~274 div:inst|Equal0~275 div:inst|Equal0~278 div:inst|divnum[0] } { 0.000ns 2.159ns 0.733ns 0.534ns 2.461ns } { 0.000ns 0.740ns 0.914ns 0.200ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 42 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "hao.bdf" "" { Schematic "E:/VERIL/shumaguan/hao.bdf" { { 40 -88 80 56 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns div:inst\|divnum\[0\] 2 REG LC_X13_Y2_N2 4 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X13_Y2_N2; Fanout = 4; REG Node = 'div:inst\|divnum\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.656 ns" { clk div:inst|divnum[0] } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk div:inst|divnum[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout div:inst|divnum[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 42 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "hao.bdf" "" { Schematic "E:/VERIL/shumaguan/hao.bdf" { { 40 -88 80 56 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns div:inst\|divnum\[8\] 2 REG LC_X16_Y2_N2 4 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X16_Y2_N2; Fanout = 4; REG Node = 'div:inst\|divnum\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.656 ns" { clk div:inst|divnum[8] } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk div:inst|divnum[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout div:inst|divnum[8] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk div:inst|divnum[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout div:inst|divnum[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk div:inst|divnum[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout div:inst|divnum[8] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.332 ns" { div:inst|divnum[8] div:inst|Equal0~274 div:inst|Equal0~275 div:inst|Equal0~278 div:inst|divnum[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.332 ns" { div:inst|divnum[8] div:inst|Equal0~274 div:inst|Equal0~275 div:inst|Equal0~278 div:inst|divnum[0] } { 0.000ns 2.159ns 0.733ns 0.534ns 2.461ns } { 0.000ns 0.740ns 0.914ns 0.200ns 0.591ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk div:inst|divnum[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout div:inst|divnum[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk div:inst|divnum[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout div:inst|divnum[8] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "jishuqi:inst1\|status4\[3\] reset clk 0.009 ns register " "Info: tsu for register \"jishuqi:inst1\|status4\[3\]\" (data pin = \"reset\", clock pin = \"clk\") is 0.009 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.353 ns + Longest pin register " "Info: + Longest pin to register delay is 8.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_93 49 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_93; Fanout = 49; PIN Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "hao.bdf" "" { Schematic "E:/VERIL/shumaguan/hao.bdf" { { 168 -24 144 184 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.542 ns) + CELL(0.200 ns) 5.874 ns jishuqi:inst1\|status4\[0\]~7 2 COMB LC_X13_Y7_N3 4 " "Info: 2: + IC(4.542 ns) + CELL(0.200 ns) = 5.874 ns; Loc. = LC_X13_Y7_N3; Fanout = 4; COMB Node = 'jishuqi:inst1\|status4\[0\]~7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.742 ns" { reset jishuqi:inst1|status4[0]~7 } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.236 ns) + CELL(1.243 ns) 8.353 ns jishuqi:inst1\|status4\[3\] 3 REG LC_X12_Y7_N3 9 " "Info: 3: + IC(1.236 ns) + CELL(1.243 ns) = 8.353 ns; Loc. = LC_X12_Y7_N3; Fanout = 9; REG Node = 'jishuqi:inst1\|status4\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.479 ns" { jishuqi:inst1|status4[0]~7 jishuqi:inst1|status4[3] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.575 ns ( 30.83 % ) " "Info: Total cell delay = 2.575 ns ( 30.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.778 ns ( 69.17 % ) " "Info: Total interconnect delay = 5.778 ns ( 69.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.353 ns" { reset jishuqi:inst1|status4[0]~7 jishuqi:inst1|status4[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.353 ns" { reset reset~combout jishuqi:inst1|status4[0]~7 jishuqi:inst1|status4[3] } { 0.000ns 0.000ns 4.542ns 1.236ns } { 0.000ns 1.132ns 0.200ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.677 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 8.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 42 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "hao.bdf" "" { Schematic "E:/VERIL/shumaguan/hao.bdf" { { 40 -88 80 56 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns div:inst\|clkout 2 REG LC_X14_Y3_N4 45 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X14_Y3_N4; Fanout = 45; REG Node = 'div:inst\|clkout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.032 ns" { clk div:inst|clkout } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.564 ns) + CELL(0.918 ns) 8.677 ns jishuqi:inst1\|status4\[3\] 3 REG LC_X12_Y7_N3 9 " "Info: 3: + IC(3.564 ns) + CELL(0.918 ns) = 8.677 ns; Loc. = LC_X12_Y7_N3; Fanout = 9; REG Node = 'jishuqi:inst1\|status4\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.482 ns" { div:inst|clkout jishuqi:inst1|status4[3] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 38.90 % ) " "Info: Total cell delay = 3.375 ns ( 38.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.302 ns ( 61.10 % ) " "Info: Total interconnect delay = 5.302 ns ( 61.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.677 ns" { clk div:inst|clkout jishuqi:inst1|status4[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.677 ns" { clk clk~combout div:inst|clkout jishuqi:inst1|status4[3] } { 0.000ns 0.000ns 1.738ns 3.564ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.353 ns" { reset jishuqi:inst1|status4[0]~7 jishuqi:inst1|status4[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.353 ns" { reset reset~combout jishuqi:inst1|status4[0]~7 jishuqi:inst1|status4[3] } { 0.000ns 0.000ns 4.542ns 1.236ns } { 0.000ns 1.132ns 0.200ns 1.243ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.677 ns" { clk div:inst|clkout jishuqi:inst1|status4[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.677 ns" { clk clk~combout div:inst|clkout jishuqi:inst1|status4[3] } { 0.000ns 0.000ns 1.738ns 3.564ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg1\[0\] jishuqi:inst1\|seg1\[0\] 14.815 ns register " "Info: tco from clock \"clk\" to destination pin \"seg1\[0\]\" through register \"jishuqi:inst1\|seg1\[0\]\" is 14.815 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.486 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 9.486 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 42 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 42; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "hao.bdf" "" { Schematic "E:/VERIL/shumaguan/hao.bdf" { { 40 -88 80 56 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns div:inst\|clkg 2 REG LC_X10_Y4_N9 15 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N9; Fanout = 15; REG Node = 'div:inst\|clkg'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.032 ns" { clk div:inst|clkg } "NODE_NAME" } } { "div.v" "" { Text "E:/VERIL/shumaguan/div.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.373 ns) + CELL(0.918 ns) 9.486 ns jishuqi:inst1\|seg1\[0\] 3 REG LC_X12_Y8_N9 1 " "Info: 3: + IC(4.373 ns) + CELL(0.918 ns) = 9.486 ns; Loc. = LC_X12_Y8_N9; Fanout = 1; REG Node = 'jishuqi:inst1\|seg1\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.291 ns" { div:inst|clkg jishuqi:inst1|seg1[0] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 35.58 % ) " "Info: Total cell delay = 3.375 ns ( 35.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.111 ns ( 64.42 % ) " "Info: Total interconnect delay = 6.111 ns ( 64.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.486 ns" { clk div:inst|clkg jishuqi:inst1|seg1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.486 ns" { clk clk~combout div:inst|clkg jishuqi:inst1|seg1[0] } { 0.000ns 0.000ns 1.738ns 4.373ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 183 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.953 ns + Longest register pin " "Info: + Longest register to pin delay is 4.953 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jishuqi:inst1\|seg1\[0\] 1 REG LC_X12_Y8_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N9; Fanout = 1; REG Node = 'jishuqi:inst1\|seg1\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { jishuqi:inst1|seg1[0] } "NODE_NAME" } } { "jishuqi.v" "" { Text "E:/VERIL/shumaguan/jishuqi.v" 183 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.631 ns) + CELL(2.322 ns) 4.953 ns seg1\[0\] 2 PIN PIN_123 0 " "Info: 2: + IC(2.631 ns) + CELL(2.322 ns) = 4.953 ns; Loc. = PIN_123; Fanout = 0; PIN Node = 'seg1\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.953 ns" { jishuqi:inst1|seg1[0] seg1[0] } "NODE_NAME" } } { "hao.bdf" "" { Schematic "E:/VERIL/shumaguan/hao.bdf" { { 40 464 640 56 "seg1\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 46.88 % ) " "Info: Total cell delay = 2.322 ns ( 46.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.631 ns ( 53.12 % ) " "Info: Total interconnect delay = 2.631 ns ( 53.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.953 ns" { jishuqi:inst1|seg1[0] seg1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.953 ns" { jishuqi:inst1|seg1[0] seg1[0] } { 0.000ns 2.631ns } { 0.000ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.486 ns" { clk div:inst|clkg jishuqi:inst1|seg1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.486 ns" { clk clk~combout div:inst|clkg jishuqi:inst1|seg1[0] } { 0.000ns 0.000ns 1.738ns 4.373ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.953 ns" { jishuqi:inst1|seg1[0] seg1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.953 ns" { jishuqi:inst1|seg1[0] seg1[0] } { 0.000ns 2.631ns } { 0.000ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}