div.v

来自「用CPLD驱动数码管」· Verilog 代码 · 共 40 行

module div(clk,clkout,clkg);
input clk;
output clkout,clkg;
reg clkout,clkg;

reg[24:0] divnum;
reg[14:0] divnum1;


always @(posedge clk)
begin
if(divnum==25000000)
begin
	divnum<=0;
	clkout=~clkout;
end
else
begin
	divnum<=divnum+1;
end
end

always @(posedge clk)
begin
if(divnum1==25000)
begin
	divnum1<=0;
	clkg=~clkg;
end
else
begin
	divnum1<=divnum1+1;
end
end





endmodule