jishuqi.v

用CPLD驱动数码管

module jishuqi(clk,clk1,rst,seg1,com1);
input clk,clk1,rst;
output[6:0] seg1;
output[3:0] com1;

reg[6:0] seg1,seg,seg2,seg3,seg4;
reg[3:0] com;

reg[1:0] status1;
reg[3:0] status,status2,status3,status4;

always @(posedge clk, posedge rst)
begin
if(rst)
begin
	status1<=2'b00;
end
else
begin
	status1<=status1+1;
end
end

always @(posedge clk,posedge rst)
begin
if(rst)
begin
	com<=4'b0000;
end
else
begin
	case(status1)
	2'b00:com<=4'b0001;
	2'b01:com<=4'b0010;
	2'b10:com<=4'b0100;
	2'b11:com<=4'b1000;
	default:com<=4'b0000;
	endcase
end
end

always @(posedge clk1,posedge rst)
begin
if(rst)
begin
status<=4'b0000;
end
else
begin
	if(status==9)
	begin
		status<=0;
		if(status2==9)
		begin
			status2<=0;
			if(status3==9)
			begin
				status3<=0;
				if(status4==9)
				begin
					status4<=0;
				end
				else
				begin
					status4<=status4+1;
				end
			end
			else
			begin
				status3<=status3+1;
			end
		end
		else
		begin
			status2<=status2+1;
		end
	end
	else
	begin
		status<=status+1;
	end
end
end

always @(posedge clk1,posedge rst)
begin
if(rst)
begin
	seg=7'b1111111;
end
else
begin
	case(status)
	4'b0000:seg<= 7'b1000000;
	4'b0001:seg<= 7'b1111001; 
	4'b0010:seg<= 7'b0100100;
	4'b0011:seg<= 7'b0110000;
	4'b0100:seg<= 7'b0011001;
	4'b0101:seg<= 7'b0010010;
	4'b0110:seg<= 7'b0000010;
	4'b0111:seg<= 7'b1111000;
	4'b1000:seg<= 7'b0000000;
	4'b1001:seg<= 7'b0011000;
	default:seg<= 7'b1000000;
	endcase
end
end

always @(posedge clk1,posedge rst)
begin
if(rst)
begin
	seg2=7'b1111111;
end
else
begin
	case(status2)
	4'b0000:seg2<= 7'b1000000;
	4'b0001:seg2<= 7'b1111001; 
	4'b0010:seg2<= 7'b0100100;
	4'b0011:seg2<= 7'b0110000;
	4'b0100:seg2<= 7'b0011001;
	4'b0101:seg2<= 7'b0010010;
	4'b0110:seg2<= 7'b0000010;
	4'b0111:seg2<= 7'b1111000;
	4'b1000:seg2<= 7'b0000000;
	4'b1001:seg2<= 7'b0011000;
	default:seg2<= 7'b1000000;
	endcase
end
end

always @(posedge clk1,posedge rst)
begin
if(rst)
begin
	seg3=7'b1111111;
end
else
begin
	case(status3)
	4'b0000:seg3<= 7'b1000000;
	4'b0001:seg3<= 7'b1111001; 
	4'b0010:seg3<= 7'b0100100;
	4'b0011:seg3<= 7'b0110000;
	4'b0100:seg3<= 7'b0011001;
	4'b0101:seg3<= 7'b0010010;
	4'b0110:seg3<= 7'b0000010;
	4'b0111:seg3<= 7'b1111000;
	4'b1000:seg3<= 7'b0000000;
	4'b1001:seg3<= 7'b0011000;
	default:seg3<= 7'b1000000;
	endcase
end
end

always @(posedge clk1,posedge rst)
begin
if(rst)
begin
	seg4=7'b1111111;
end
else
begin
	case(status4)
	4'b0000:seg4<= 7'b1000000;
	4'b0001:seg4<= 7'b1111001; 
	4'b0010:seg4<= 7'b0100100;
	4'b0011:seg4<= 7'b0110000;
	4'b0100:seg4<= 7'b0011001;
	4'b0101:seg4<= 7'b0010010;
	4'b0110:seg4<= 7'b0000010;
	4'b0111:seg4<= 7'b1111000;
	4'b1000:seg4<= 7'b0000000;
	4'b1001:seg4<= 7'b0011000;
	default:seg4<= 7'b1000000;
	endcase
end
end

always @(posedge clk, posedge rst)
begin
if(rst)
begin
	seg1<=7'b1111111;
end
else
begin
if(com==4'b0001)
begin
	seg1<=seg2;
end
else if(com==4'b0010)
begin
	seg1<=seg3;
end
else if(com==4'b0100)
begin
	seg1<=seg4;
end
else if(com==4'b1000)
begin
	seg1<=seg;
end
end
end
	
assign com1=com;

endmodule