hao.map.rpt

用CPLD驱动数码管

; Total fan-out                               ; 649   ;
; Average fan-out                             ; 3.59  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |hao                       ; 168 (0)     ; 100          ; 0          ; 13   ; 0            ; 68 (0)       ; 20 (0)            ; 80 (0)           ; 40 (0)          ; 0 (0)      ; |hao                ;
;    |div:inst|              ; 94 (94)     ; 42           ; 0          ; 0    ; 0            ; 52 (52)      ; 20 (20)           ; 22 (22)          ; 40 (40)         ; 0 (0)      ; |hao|div:inst       ;
;    |jishuqi:inst1|         ; 74 (74)     ; 58           ; 0          ; 0    ; 0            ; 16 (16)      ; 0 (0)             ; 58 (58)          ; 0 (0)           ; 0 (0)      ; |hao|jishuqi:inst1  ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------+
; State Machine - |hao|jishuqi:inst1|com                          ;
+----------+----------+----------+----------+----------+----------+
; Name     ; com.0000 ; com.1000 ; com.0100 ; com.0010 ; com.0001 ;
+----------+----------+----------+----------+----------+----------+
; com.0000 ; 0        ; 0        ; 0        ; 0        ; 0        ;
; com.0100 ; 1        ; 0        ; 1        ; 0        ; 0        ;
; com.0010 ; 1        ; 0        ; 0        ; 1        ; 0        ;
; com.0001 ; 1        ; 0        ; 0        ; 0        ; 1        ;
; com.1000 ; 1        ; 1        ; 0        ; 0        ; 0        ;
+----------+----------+----------+----------+----------+----------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 100   ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 46    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 16    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------+
; Inverted Register Statistics                      ;
+-----------------------------------------+---------+
; Inverted Register                       ; Fan out ;
+-----------------------------------------+---------+
; jishuqi:inst1|seg1[6]                   ; 1       ;
; jishuqi:inst1|seg1[5]                   ; 1       ;
; jishuqi:inst1|seg1[4]                   ; 1       ;
; jishuqi:inst1|seg1[3]                   ; 1       ;
; jishuqi:inst1|seg1[2]                   ; 1       ;
; jishuqi:inst1|seg1[1]                   ; 1       ;
; jishuqi:inst1|seg1[0]                   ; 1       ;
; jishuqi:inst1|seg3[6]                   ; 1       ;
; jishuqi:inst1|seg4[6]                   ; 1       ;
; jishuqi:inst1|seg[6]                    ; 1       ;
; jishuqi:inst1|seg2[6]                   ; 1       ;
; jishuqi:inst1|seg4[5]                   ; 1       ;
; jishuqi:inst1|seg3[5]                   ; 1       ;
; jishuqi:inst1|seg[5]                    ; 1       ;
; jishuqi:inst1|seg2[5]                   ; 1       ;
; jishuqi:inst1|seg3[4]                   ; 1       ;
; jishuqi:inst1|seg4[4]                   ; 1       ;
; jishuqi:inst1|seg[4]                    ; 1       ;
; jishuqi:inst1|seg2[4]                   ; 1       ;
; jishuqi:inst1|seg4[3]                   ; 1       ;
; jishuqi:inst1|seg3[3]                   ; 1       ;
; jishuqi:inst1|seg[3]                    ; 1       ;
; jishuqi:inst1|seg2[3]                   ; 1       ;
; jishuqi:inst1|seg3[2]                   ; 1       ;
; jishuqi:inst1|seg4[2]                   ; 1       ;
; jishuqi:inst1|seg[2]                    ; 1       ;
; jishuqi:inst1|seg2[2]                   ; 1       ;
; jishuqi:inst1|seg4[1]                   ; 1       ;
; jishuqi:inst1|seg3[1]                   ; 1       ;
; jishuqi:inst1|seg[1]                    ; 1       ;
; jishuqi:inst1|seg2[1]                   ; 1       ;
; jishuqi:inst1|seg3[0]                   ; 1       ;
; jishuqi:inst1|seg4[0]                   ; 1       ;
; jishuqi:inst1|seg[0]                    ; 1       ;
; jishuqi:inst1|seg2[0]                   ; 1       ;
; Total number of inverted registers = 35 ;         ;
+-----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 5:1                ; 7 bits    ; 21 LEs        ; 14 LEs               ; 7 LEs                  ; Yes        ; |hao|jishuqi:inst1|seg1[5] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Aug 25 16:52:43 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hao -c hao
Info: Found 1 design units, including 1 entities, in source file hao.bdf
    Info: Found entity 1: hao
Info: Elaborating entity "hao" for the top level hierarchy
Warning: Using design file jishuqi.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: jishuqi
Info: Elaborating entity "jishuqi" for hierarchy "jishuqi:inst1"
Warning (10230): Verilog HDL assignment warning at jishuqi.v(20): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at jishuqi.v(65): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at jishuqi.v(70): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at jishuqi.v(75): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at jishuqi.v(80): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at jishuqi.v(208): truncated value with size 5 to match size of target (4)
Warning: Using design file div.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: div
Info: Elaborating entity "div" for hierarchy "div:inst"
Warning (10230): Verilog HDL assignment warning at div.v(19): truncated value with size 32 to match size of target (25)
Warning (10230): Verilog HDL assignment warning at div.v(32): truncated value with size 32 to match size of target (15)
Info: State machine "|hao|jishuqi:inst1|com" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|hao|jishuqi:inst1|com"
Info: Encoding result for state machine "|hao|jishuqi:inst1|com"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "jishuqi:inst1|com.0000"
        Info: Encoded state bit "jishuqi:inst1|com.1000"
        Info: Encoded state bit "jishuqi:inst1|com.0100"
        Info: Encoded state bit "jishuqi:inst1|com.0010"
        Info: Encoded state bit "jishuqi:inst1|com.0001"
    Info: State "|hao|jishuqi:inst1|com.0000" uses code string "00000"
    Info: State "|hao|jishuqi:inst1|com.0100" uses code string "10100"
    Info: State "|hao|jishuqi:inst1|com.0010" uses code string "10010"
    Info: State "|hao|jishuqi:inst1|com.0001" uses code string "10001"
    Info: State "|hao|jishuqi:inst1|com.1000" uses code string "11000"
Info: Registers with preset signals will power-up high
Info: Implemented 181 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 11 output pins
    Info: Implemented 168 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Sat Aug 25 16:52:46 2007
    Info: Elapsed time: 00:00:04


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/VERIL/shumaguan/hao.map.smsg.