jishuqi.map.summary

来自「用CPLD驱动数码管」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Sat Aug 25 15:59:28 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : jishuqi
Top-level Entity Name : jishuqi
Family : Stratix
Total logic elements : 75
Total pins : 14
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0