div.fit.rpt

用CPLD驱动数码管

+--------------------------------------------------------------------------------+----------+
; Name                                                                           ; Value    ;
+--------------------------------------------------------------------------------+----------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff       ;
; Mid Wire Use - Fit Attempt 1                                                   ; 4        ;
; Mid Slack - Fit Attempt 1                                                      ; -10109   ;
; Internal Atom Count - Fit Attempt 1                                            ; 84       ;
; LE/ALM Count - Fit Attempt 1                                                   ; 84       ;
; LAB Count - Fit Attempt 1                                                      ; 12       ;
; Outputs per Lab - Fit Attempt 1                                                ; 6.167    ;
; Inputs per LAB - Fit Attempt 1                                                 ; 7.083    ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.917    ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:12     ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:12     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:12     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:12     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:12     ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:12     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:12     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:12     ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:12     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:1;1:11 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:1;1:11 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:12     ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:1;1:11 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:7;1:5  ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:4;1:8  ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:7;1:5  ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:12     ;
; LEs in Chains - Fit Attempt 1                                                  ; 40       ;
; LEs in Long Chains - Fit Attempt 1                                             ; 40       ;
; LABs with Chains - Fit Attempt 1                                               ; 5        ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0        ;
; Time - Fit Attempt 1                                                           ; 0        ;
+--------------------------------------------------------------------------------+----------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 1      ;
; Early Slack - Fit Attempt 1         ; -15831 ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 2      ;
; Mid Slack - Fit Attempt 1           ; -9117  ;
; Late Wire Use - Fit Attempt 1       ; 2      ;
; Late Slack - Fit Attempt 1          ; -9117  ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.189  ;
+-------------------------------------+--------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1         ; -8053 ;
; Early Wire Use - Fit Attempt 1      ; 1     ;
; Peak Regional Wire - Fit Attempt 1  ; 1     ;
; Mid Slack - Fit Attempt 1           ; -8195 ;
; Late Slack - Fit Attempt 1          ; -8195 ;
; Late Slack - Fit Attempt 1          ; -8195 ;
; Late Wire Use - Fit Attempt 1       ; 2     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.125 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Aug 25 16:02:50 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off div -c div
Info: Selected device EPM1270T144C5 for design "div"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM570T144I5 is compatible
    Info: Device EPM1270T144I5 is compatible
Info: No exact pin location assignment(s) for 3 pins of 3 total pins
    Info: Pin clkout not assigned to an exact location on the device
    Info: Pin clkg not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 2 (unused VREF, 3.30 VCCIO, 0 input, 2 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  25 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 7.783 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y8; Fanout = 4; REG Node = 'divnum[4]'
    Info: 2: + IC(2.045 ns) + CELL(0.978 ns) = 3.023 ns; Loc. = LAB_X8_Y8; Fanout = 2; COMB Node = 'Add0~411'
    Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 3.146 ns; Loc. = LAB_X8_Y8; Fanout = 2; COMB Node = 'Add0~409'
    Info: 4: + IC(0.000 ns) + CELL(0.399 ns) = 3.545 ns; Loc. = LAB_X8_Y8; Fanout = 6; COMB Node = 'Add0~405'
    Info: 5: + IC(0.000 ns) + CELL(0.246 ns) = 3.791 ns; Loc. = LAB_X9_Y8; Fanout = 6; COMB Node = 'Add0~397'
    Info: 6: + IC(0.000 ns) + CELL(0.246 ns) = 4.037 ns; Loc. = LAB_X9_Y8; Fanout = 6; COMB Node = 'Add0~385'
    Info: 7: + IC(0.000 ns) + CELL(1.234 ns) = 5.271 ns; Loc. = LAB_X10_Y8; Fanout = 1; COMB Node = 'Add0~380'
    Info: 8: + IC(1.329 ns) + CELL(1.183 ns) = 7.783 ns; Loc. = LAB_X12_Y8; Fanout = 4; REG Node = 'divnum[19]'
    Info: Total cell delay = 4.409 ns ( 56.65 % )
    Info: Total interconnect delay = 3.374 ns ( 43.35 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 1%
    Info: The peak interconnect region extends from location x9_y0 to location x17_y11
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Sat Aug 25 16:02:53 2007
    Info: Elapsed time: 00:00:04


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/VERIL/shumaguan/div.fit.smsg.