beep.tan.qmsg

用CPLD驱动扬声器实现音乐的播放

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "beep.bdf" "" { Schematic "E:/VERIL/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register buzzer:inst\|clk_div2\[8\] register buzzer:inst\|clk_div2\[5\] 61.72 MHz 16.201 ns Internal " "Info: Clock \"clk\" has Internal fmax of 61.72 MHz between source register \"buzzer:inst\|clk_div2\[8\]\" and destination register \"buzzer:inst\|clk_div2\[5\]\" (period= 16.201 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.492 ns + Longest register register " "Info: + Longest register to register delay is 15.492 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buzzer:inst\|clk_div2\[8\] 1 REG LC_X13_Y5_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y5_N2; Fanout = 8; REG Node = 'buzzer:inst\|clk_div2\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { buzzer:inst|clk_div2[8] } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.297 ns) + CELL(0.511 ns) 2.808 ns buzzer:inst\|Equal5~93 2 COMB LC_X12_Y6_N7 2 " "Info: 2: + IC(2.297 ns) + CELL(0.511 ns) = 2.808 ns; Loc. = LC_X12_Y6_N7; Fanout = 2; COMB Node = 'buzzer:inst\|Equal5~93'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.808 ns" { buzzer:inst|clk_div2[8] buzzer:inst|Equal5~93 } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.849 ns) + CELL(0.200 ns) 4.857 ns buzzer:inst\|Equal6~108 3 COMB LC_X12_Y5_N2 2 " "Info: 3: + IC(1.849 ns) + CELL(0.200 ns) = 4.857 ns; Loc. = LC_X12_Y5_N2; Fanout = 2; COMB Node = 'buzzer:inst\|Equal6~108'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.049 ns" { buzzer:inst|Equal5~93 buzzer:inst|Equal6~108 } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.710 ns) + CELL(0.200 ns) 5.767 ns buzzer:inst\|Equal7~90 4 COMB LC_X12_Y5_N0 2 " "Info: 4: + IC(0.710 ns) + CELL(0.200 ns) = 5.767 ns; Loc. = LC_X12_Y5_N0; Fanout = 2; COMB Node = 'buzzer:inst\|Equal7~90'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.910 ns" { buzzer:inst|Equal6~108 buzzer:inst|Equal7~90 } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.240 ns) + CELL(0.511 ns) 7.518 ns buzzer:inst\|Equal7~92 5 COMB LC_X11_Y5_N5 2 " "Info: 5: + IC(1.240 ns) + CELL(0.511 ns) = 7.518 ns; Loc. = LC_X11_Y5_N5; Fanout = 2; COMB Node = 'buzzer:inst\|Equal7~92'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.751 ns" { buzzer:inst|Equal7~90 buzzer:inst|Equal7~92 } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.511 ns) 8.811 ns buzzer:inst\|clk_div2\[6\]~2052 6 COMB LC_X11_Y5_N2 1 " "Info: 6: + IC(0.782 ns) + CELL(0.511 ns) = 8.811 ns; Loc. = LC_X11_Y5_N2; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2052'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.293 ns" { buzzer:inst|Equal7~92 buzzer:inst|clk_div2[6]~2052 } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 9.316 ns buzzer:inst\|clk_div2\[6\]~2046 7 COMB LC_X11_Y5_N3 1 " "Info: 7: + IC(0.305 ns) + CELL(0.200 ns) = 9.316 ns; Loc. = LC_X11_Y5_N3; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2046'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { buzzer:inst|clk_div2[6]~2052 buzzer:inst|clk_div2[6]~2046 } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.696 ns) + CELL(0.200 ns) 11.212 ns buzzer:inst\|clk_div2\[6\]~2047 8 COMB LC_X13_Y5_N9 1 " "Info: 8: + IC(1.696 ns) + CELL(0.200 ns) = 11.212 ns; Loc. = LC_X13_Y5_N9; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2047'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.896 ns" { buzzer:inst|clk_div2[6]~2046 buzzer:inst|clk_div2[6]~2047 } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.200 ns) 12.141 ns buzzer:inst\|clk_div2\[6\]~2048 9 COMB LC_X13_Y5_N7 1 " "Info: 9: + IC(0.729 ns) + CELL(0.200 ns) = 12.141 ns; Loc. = LC_X13_Y5_N7; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2048'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.929 ns" { buzzer:inst|clk_div2[6]~2047 buzzer:inst|clk_div2[6]~2048 } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 12.646 ns buzzer:inst\|clk_div2\[6\]~2049 10 COMB LC_X13_Y5_N8 13 " "Info: 10: + IC(0.305 ns) + CELL(0.200 ns) = 12.646 ns; Loc. = LC_X13_Y5_N8; Fanout = 13; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2049'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { buzzer:inst|clk_div2[6]~2048 buzzer:inst|clk_div2[6]~2049 } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.086 ns) + CELL(1.760 ns) 15.492 ns buzzer:inst\|clk_div2\[5\] 11 REG LC_X12_Y5_N9 7 " "Info: 11: + IC(1.086 ns) + CELL(1.760 ns) = 15.492 ns; Loc. = LC_X12_Y5_N9; Fanout = 7; REG Node = 'buzzer:inst\|clk_div2\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.846 ns" { buzzer:inst|clk_div2[6]~2049 buzzer:inst|clk_div2[5] } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.493 ns ( 29.00 % ) " "Info: Total cell delay = 4.493 ns ( 29.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.999 ns ( 71.00 % ) " "Info: Total interconnect delay = 10.999 ns ( 71.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.492 ns" { buzzer:inst|clk_div2[8] buzzer:inst|Equal5~93 buzzer:inst|Equal6~108 buzzer:inst|Equal7~90 buzzer:inst|Equal7~92 buzzer:inst|clk_div2[6]~2052 buzzer:inst|clk_div2[6]~2046 buzzer:inst|clk_div2[6]~2047 buzzer:inst|clk_div2[6]~2048 buzzer:inst|clk_div2[6]~2049 buzzer:inst|clk_div2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "15.492 ns" { buzzer:inst|clk_div2[8] buzzer:inst|Equal5~93 buzzer:inst|Equal6~108 buzzer:inst|Equal7~90 buzzer:inst|Equal7~92 buzzer:inst|clk_div2[6]~2052 buzzer:inst|clk_div2[6]~2046 buzzer:inst|clk_div2[6]~2047 buzzer:inst|clk_div2[6]~2048 buzzer:inst|clk_div2[6]~2049 buzzer:inst|clk_div2[5] } { 0.000ns 2.297ns 1.849ns 0.710ns 1.240ns 0.782ns 0.305ns 1.696ns 0.729ns 0.305ns 1.086ns } { 0.000ns 0.511ns 0.200ns 0.200ns 0.511ns 0.511ns 0.200ns 0.200ns 0.200ns 0.200ns 1.760ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 48 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 48; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "beep.bdf" "" { Schematic "E:/VERIL/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns buzzer:inst\|clk_div2\[5\] 2 REG LC_X12_Y5_N9 7 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X12_Y5_N9; Fanout = 7; REG Node = 'buzzer:inst\|clk_div2\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.656 ns" { clk buzzer:inst|clk_div2[5] } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk buzzer:inst|clk_div2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[5] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 48 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 48; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "beep.bdf" "" { Schematic "E:/VERIL/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns buzzer:inst\|clk_div2\[8\] 2 REG LC_X13_Y5_N2 8 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X13_Y5_N2; Fanout = 8; REG Node = 'buzzer:inst\|clk_div2\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.656 ns" { clk buzzer:inst|clk_div2[8] } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk buzzer:inst|clk_div2[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[8] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk buzzer:inst|clk_div2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[5] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk buzzer:inst|clk_div2[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[8] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.492 ns" { buzzer:inst|clk_div2[8] buzzer:inst|Equal5~93 buzzer:inst|Equal6~108 buzzer:inst|Equal7~90 buzzer:inst|Equal7~92 buzzer:inst|clk_div2[6]~2052 buzzer:inst|clk_div2[6]~2046 buzzer:inst|clk_div2[6]~2047 buzzer:inst|clk_div2[6]~2048 buzzer:inst|clk_div2[6]~2049 buzzer:inst|clk_div2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "15.492 ns" { buzzer:inst|clk_div2[8] buzzer:inst|Equal5~93 buzzer:inst|Equal6~108 buzzer:inst|Equal7~90 buzzer:inst|Equal7~92 buzzer:inst|clk_div2[6]~2052 buzzer:inst|clk_div2[6]~2046 buzzer:inst|clk_div2[6]~2047 buzzer:inst|clk_div2[6]~2048 buzzer:inst|clk_div2[6]~2049 buzzer:inst|clk_div2[5] } { 0.000ns 2.297ns 1.849ns 0.710ns 1.240ns 0.782ns 0.305ns 1.696ns 0.729ns 0.305ns 1.086ns } { 0.000ns 0.511ns 0.200ns 0.200ns 0.511ns 0.511ns 0.200ns 0.200ns 0.200ns 0.200ns 1.760ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk buzzer:inst|clk_div2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[5] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk buzzer:inst|clk_div2[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[8] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "buzzer:inst\|clk_div2\[5\] reset clk 6.533 ns register " "Info: tsu for register \"buzzer:inst\|clk_div2\[5\]\" (data pin = \"reset\", clock pin = \"clk\") is 6.533 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.019 ns + Longest pin register " "Info: + Longest pin to register delay is 10.019 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_93 36 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_93; Fanout = 36; PIN Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "beep.bdf" "" { Schematic "E:/VERIL/beep/beep.bdf" { { 176 72 240 192 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.142 ns) + CELL(0.511 ns) 3.785 ns buzzer:inst\|clk_div2\[6\]~2042 2 COMB LC_X13_Y6_N1 1 " "Info: 2: + IC(2.142 ns) + CELL(0.511 ns) = 3.785 ns; Loc. = LC_X13_Y6_N1; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2042'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.653 ns" { reset buzzer:inst|clk_div2[6]~2042 } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.290 ns buzzer:inst\|clk_div2\[6\]~2043 3 COMB LC_X13_Y6_N2 1 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 4.290 ns; Loc. = LC_X13_Y6_N2; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2043'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { buzzer:inst|clk_div2[6]~2042 buzzer:inst|clk_div2[6]~2043 } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.795 ns buzzer:inst\|clk_div2\[6\]~2044 4 COMB LC_X13_Y6_N3 1 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 4.795 ns; Loc. = LC_X13_Y6_N3; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2044'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { buzzer:inst|clk_div2[6]~2043 buzzer:inst|clk_div2[6]~2044 } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.867 ns) + CELL(0.511 ns) 7.173 ns buzzer:inst\|clk_div2\[6\]~2049 5 COMB LC_X13_Y5_N8 13 " "Info: 5: + IC(1.867 ns) + CELL(0.511 ns) = 7.173 ns; Loc. = LC_X13_Y5_N8; Fanout = 13; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2049'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.378 ns" { buzzer:inst|clk_div2[6]~2044 buzzer:inst|clk_div2[6]~2049 } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.086 ns) + CELL(1.760 ns) 10.019 ns buzzer:inst\|clk_div2\[5\] 6 REG LC_X12_Y5_N9 7 " "Info: 6: + IC(1.086 ns) + CELL(1.760 ns) = 10.019 ns; Loc. = LC_X12_Y5_N9; Fanout = 7; REG Node = 'buzzer:inst\|clk_div2\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.846 ns" { buzzer:inst|clk_div2[6]~2049 buzzer:inst|clk_div2[5] } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.314 ns ( 43.06 % ) " "Info: Total cell delay = 4.314 ns ( 43.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.705 ns ( 56.94 % ) " "Info: Total interconnect delay = 5.705 ns ( 56.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.019 ns" { reset buzzer:inst|clk_div2[6]~2042 buzzer:inst|clk_div2[6]~2043 buzzer:inst|clk_div2[6]~2044 buzzer:inst|clk_div2[6]~2049 buzzer:inst|clk_div2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.019 ns" { reset reset~combout buzzer:inst|clk_div2[6]~2042 buzzer:inst|clk_div2[6]~2043 buzzer:inst|clk_div2[6]~2044 buzzer:inst|clk_div2[6]~2049 buzzer:inst|clk_div2[5] } { 0.000ns 0.000ns 2.142ns 0.305ns 0.305ns 1.867ns 1.086ns } { 0.000ns 1.132ns 0.511ns 0.200ns 0.200ns 0.511ns 1.760ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 48 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 48; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "beep.bdf" "" { Schematic "E:/VERIL/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns buzzer:inst\|clk_div2\[5\] 2 REG LC_X12_Y5_N9 7 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X12_Y5_N9; Fanout = 7; REG Node = 'buzzer:inst\|clk_div2\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.656 ns" { clk buzzer:inst|clk_div2[5] } "NODE_NAME" } } { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk buzzer:inst|clk_div2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[5] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.019 ns" { reset buzzer:inst|clk_div2[6]~2042 buzzer:inst|clk_div2[6]~2043 buzzer:inst|clk_div2[6]~2044 buzzer:inst|clk_div2[6]~2049 buzzer:inst|clk_div2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.019 ns" { reset reset~combout buzzer:inst|clk_div2[6]~2042 buzzer:inst|clk_div2[6]~2043 buzzer:inst|clk_div2[6]~2044 buzzer:inst|clk_div2[6]~2049 buzzer:inst|clk_div2[5] } { 0.000ns 0.000ns 2.142ns 0.305ns 0.305ns 1.867ns 1.086ns } { 0.000ns 1.132ns 0.511ns 0.200ns 0.200ns 0.511ns 1.760ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk buzzer:inst|clk_div2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[5] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}