beep.map.qmsg

用CPLD驱动扬声器实现音乐的播放

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 06 20:10:14 2007 " "Info: Processing started: Tue Nov 06 20:10:14 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off beep -c beep " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off beep -c beep" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "beep.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file beep.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 beep " "Info: Found entity 1: beep" {  } { { "beep.bdf" "" { Schematic "E:/VERIL/beep/beep.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "buzzer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file buzzer.v" { { "Info" "ISGN_ENTITY_NAME" "1 buzzer " "Info: Found entity 1: buzzer" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "beep " "Info: Elaborating entity \"beep\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "buzzer buzzer:inst " "Info: Elaborating entity \"buzzer\" for hierarchy \"buzzer:inst\"" {  } { { "beep.bdf" "inst" { Schematic "E:/VERIL/beep/beep.bdf" { { 136 312 408 232 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(51) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(51): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 51 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(55) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(55): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 55 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(62) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(62): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 62 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(66) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(66): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(73) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(73): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(77) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(77): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(84) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(84): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 84 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(88) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(88): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 88 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(95) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(95): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 95 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(99) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(99): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 99 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(106) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(106): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 106 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(110) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(110): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 110 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(117) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(117): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 117 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(121) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(121): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 121 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(128) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(128): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 128 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(132) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(132): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 132 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|beep\|buzzer:inst\|state 8 " "Info: State machine \"\|beep\|buzzer:inst\|state\" contains 8 states" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|beep\|buzzer:inst\|state " "Info: Selected Auto state machine encoding method for state machine \"\|beep\|buzzer:inst\|state\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|beep\|buzzer:inst\|state " "Info: Encoding result for state machine \"\|beep\|buzzer:inst\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "8 " "Info: Completed encoding using 8 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.111 " "Info: Encoded state bit \"buzzer:inst\|state.111\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.001 " "Info: Encoded state bit \"buzzer:inst\|state.001\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.010 " "Info: Encoded state bit \"buzzer:inst\|state.010\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.011 " "Info: Encoded state bit \"buzzer:inst\|state.011\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.100 " "Info: Encoded state bit \"buzzer:inst\|state.100\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.101 " "Info: Encoded state bit \"buzzer:inst\|state.101\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.110 " "Info: Encoded state bit \"buzzer:inst\|state.110\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.000 " "Info: Encoded state bit \"buzzer:inst\|state.000\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.000 00000000 " "Info: State \"\|beep\|buzzer:inst\|state.000\" uses code string \"00000000\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.110 00000011 " "Info: State \"\|beep\|buzzer:inst\|state.110\" uses code string \"00000011\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.101 00000101 " "Info: State \"\|beep\|buzzer:inst\|state.101\" uses code string \"00000101\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.100 00001001 " "Info: State \"\|beep\|buzzer:inst\|state.100\" uses code string \"00001001\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.011 00010001 " "Info: State \"\|beep\|buzzer:inst\|state.011\" uses code string \"00010001\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.010 00100001 " "Info: State \"\|beep\|buzzer:inst\|state.010\" uses code string \"00100001\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.001 01000001 " "Info: State \"\|beep\|buzzer:inst\|state.001\" uses code string \"01000001\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.111 10000001 " "Info: State \"\|beep\|buzzer:inst\|state.111\" uses code string \"10000001\"" {  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "buzzer.v" "" { Text "E:/VERIL/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "107 " "Info: Implemented 107 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "104 " "Info: Implemented 104 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 06 20:10:17 2007 " "Info: Processing ended: Tue Nov 06 20:10:17 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}