ilx509_driver.tan.qmsg

来自「本文件是用CPLD（EPM7064）驱动线阵CCD（ILX509）」· QMSG 代码 · 共 11 行 · 第 1/2 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "ROG~reg0 " "Info: Detected ripple clock \"ROG~reg0\" as buffer" {  } { { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 46 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ROG~reg0" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register NUM\[1\] register ROG~reg0 92.59 MHz 10.8 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 92.59 MHz between source register \"NUM\[1\]\" and destination register \"ROG~reg0\" (period= 10.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.800 ns + Longest register register " "Info: + Longest register to register delay is 6.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns NUM\[1\] 1 REG LC32 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC32; Fanout = 26; REG Node = 'NUM\[1\]'" {  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "" { NUM[1] } "NODE_NAME" } "" } } { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns ROG~13 2 COMB LC56 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC56; Fanout = 1; COMB Node = 'ROG~13'" {  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "6.000 ns" { NUM[1] ROG~13 } "NODE_NAME" } "" } } { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 6.800 ns ROG~reg0 3 REG LC57 12 " "Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 6.800 ns; Loc. = LC57; Fanout = 12; REG Node = 'ROG~reg0'" {  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "0.800 ns" { ROG~13 ROG~reg0 } "NODE_NAME" } "" } } { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns 85.29 % " "Info: Total cell delay = 5.800 ns ( 85.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 14.71 % " "Info: Total interconnect delay = 1.000 ns ( 14.71 % )" {  } {  } 0}  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "6.800 ns" { NUM[1] ROG~13 ROG~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.800 ns" { NUM[1] ROG~13 ROG~reg0 } { 0.000ns 1.000ns 0.000ns } { 0.000ns 5.000ns 0.800ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.500 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_37 25 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_37; Fanout = 25; CLK Node = 'CLK'" {  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns ROG~reg0 2 REG LC57 12 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC57; Fanout = 12; REG Node = 'ROG~reg0'" {  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "6.000 ns" { CLK ROG~reg0 } "NODE_NAME" } "" } } { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 46 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "6.500 ns" { CLK ROG~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { CLK CLK~out ROG~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 6.500 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_37 25 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_37; Fanout = 25; CLK Node = 'CLK'" {  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns NUM\[1\] 2 REG LC32 26 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC32; Fanout = 26; REG Node = 'NUM\[1\]'" {  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "6.000 ns" { CLK NUM[1] } "NODE_NAME" } "" } } { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "6.500 ns" { CLK NUM[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { CLK CLK~out NUM[1] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "6.500 ns" { CLK ROG~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { CLK CLK~out ROG~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "6.500 ns" { CLK NUM[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { CLK CLK~out NUM[1] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 46 -1 0 } }  } 0}  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "6.800 ns" { NUM[1] ROG~13 ROG~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.800 ns" { NUM[1] ROG~13 ROG~reg0 } { 0.000ns 1.000ns 0.000ns } { 0.000ns 5.000ns 0.800ns } } } { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "6.500 ns" { CLK ROG~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { CLK CLK~out ROG~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "6.500 ns" { CLK NUM[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { CLK CLK~out NUM[1] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK LED LED~reg0 18.000 ns register " "Info: tco from clock \"CLK\" to destination pin \"LED\" through register \"LED~reg0\" is 18.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 14.500 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 14.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_37 25 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_37; Fanout = 25; CLK Node = 'CLK'" {  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "" { CLK } "NODE_NAME" } "" } } { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.500 ns ROG~reg0 2 REG LC57 12 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.500 ns; Loc. = LC57; Fanout = 12; REG Node = 'ROG~reg0'" {  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "8.000 ns" { CLK ROG~reg0 } "NODE_NAME" } "" } } { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 46 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.500 ns LED~reg0 3 REG LC46 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = LC46; Fanout = 1; REG Node = 'LED~reg0'" {  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "6.000 ns" { ROG~reg0 LED~reg0 } "NODE_NAME" } "" } } { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 62 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.500 ns 86.21 % " "Info: Total cell delay = 12.500 ns ( 86.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 13.79 % " "Info: Total interconnect delay = 2.000 ns ( 13.79 % )" {  } {  } 0}  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "14.500 ns" { CLK ROG~reg0 LED~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "14.500 ns" { CLK CLK~out ROG~reg0 LED~reg0 } { 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 7.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 62 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns + Longest register pin " "Info: + Longest register to pin delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LED~reg0 1 REG LC46 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC46; Fanout = 1; REG Node = 'LED~reg0'" {  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "" { LED~reg0 } "NODE_NAME" } "" } } { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 62 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns LED 2 PIN PIN_31 0 " "Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'LED'" {  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "1.500 ns" { LED~reg0 LED } "NODE_NAME" } "" } } { "CNT20.VHD" "" { Text "H:/MyDesigns/SOPCprojects/ILX509_Driver/CNT20.VHD" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "1.500 ns" { LED~reg0 LED } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { LED~reg0 LED } { 0.000ns 0.000ns } { 0.000ns 1.500ns } } }  } 0}  } { { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "14.500 ns" { CLK ROG~reg0 LED~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "14.500 ns" { CLK CLK~out ROG~reg0 LED~reg0 } { 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 0.500ns 7.000ns 5.000ns } } } { "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" "" { Report "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver_cmp.qrpt" Compiler "ILX509_Driver" "UNKNOWN" "V1" "H:/MyDesigns/SOPCprojects/ILX509_Driver/db/ILX509_Driver.quartus_db" { Floorplan "H:/MyDesigns/SOPCprojects/ILX509_Driver/" "" "1.500 ns" { LED~reg0 LED } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { LED~reg0 LED } { 0.000ns 0.000ns } { 0.000ns 1.500ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 29 09:54:18 2006 " "Info: Processing ended: Sat Apr 29 09:54:18 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}